Method for clock synchronization validation in integrated circuit design
View Patent ↗Unsynchronized clock-domain crossings in the design of integrated circuit are detected by searching for clock-crossing domains. For each clock-crossing that does not include an explicit synchronization cell, an analysis determines if the clock is stable crossing the domains.
1. A method for detecting unstable clock-domain crossings in a design of an integrated circuit (IC), comprising:
determining clock-domain crossings in the design and;
making a stability determination for a clock-domain crossing lacking a structural synchronization cell determined in the design,
wherein the stability determination is made based on satisfaction of a stability function.
2. The method of claim 1 , wherein the stability function determines whether a first register and a second register change data simultaneously.
3. The method of claim 2 , wherein the stability function is dissatisfied when the first register and the second register change data simultaneously.
4. The method of claim 3 , wherein the first register belongs to a first clock domain and the second register belongs to a second clock domain, and the first clock-domain and the second clock domain are part of the determined clock-domain crossing.
5. The method of claim 1 , wherein the stability determination is performed using at least one of model checking and bounded model checking (BMC).
6. A computer program product, including a computer readable medium with computer instructions, for use by a computer to perform operations for detecting unstable clock-domain crossings in a design of an integrated circuit (IC), the operations comprising:
determining clock-domain crossings in the design; and
making a stability determination for a clock-domain crossing lacking a structural synchronization cell determined in the design,
wherein the stability determination is made based on satisfaction of a stability function.
7. The computer program product of claim 6 , wherein the stability function determines whether a first register and a second register change data simultaneously.
8. The computer program product of claim 7 , wherein the stability function is dissatisfied when the first register and the second register change data simultaneously.
9. The computer program product of claim 8 , wherein the first register belongs to a first clock domain and the second register belongs to a second clock domain, and the first clock-domain and the second clock domain are part of the determined clock-domain crossing.
10. The computer program product of claim 6 , wherein the stability determination is performed using at least one of model checking and bounded model checking (BMC).
11. A computer system, adapted to implement a method for detecting unstable clock-domain crossings in a design of an integrated circuit (IC), comprising:
a processor; and
a memory including software instructions adapted to enable the computer system to perform the operations of:
determining clock-domain crossings in the design; and
making a stability determination for the clock-domain crossing lacking a structural synchronization cell determined in the design,
wherein the stability determination is made based on satisfaction of a stability function.
12. The computer system of claim 11 , wherein the stability function determines whether a first register and a second register change data simultaneously.
13. The computer system of claim 12 , wherein the stability function is dissatisfied when the first register and the second register change data simultaneously.
14. The computer system of claim 13 , wherein the first register belongs to a first clock domain and the second register belongs to a second clock domain, and the first clock-domain and the second clock domain are part of the determined clock-domain crossing.
15. The computer system of claim 11 , wherein the stability determination is performed using at least one of model checking and bounded model checking (BMC).