Patent Assignment
Reel/Frame 036584/0644
Release of Security Interest
Recorded: 2015-09-10
Pages: 16
Assignor
SILICON VALLEY BANK
Executed: 2015-08-25
Assignee
ATRENTA INC.
2077 GATEWAY PL, SAN JOSE, CALIFORNIA, 95110
Covered Properties
(76)
Apparatus and Method for Handling of Multi-Level Circuit Design Data
Method for Detecting Bus Contention from Rtl Description
Method for Determining Fault Coverage from Rtl Description
Identification and Implementation of Clock Gating in the Design of Integrated Circuits
Method for Clock Synchronization Validation in Integrated Circuit Design
A Method, System, and Computer Program Product for Generating and Verifying Isolation Logic Modules in Design of Integrated Circuits
A Method, System, and Computer Program Product for Automatic Insertion and Correctness Verification of Level Shifters in Integrated Circuits with Multiple Voltage Domains
Pattern Recognition in an Integrated Circuit Design
Chip Development System Enabled for the Handling of Multi-Level Circuit Design Data
Method for Clock Synchronization Validation in Integrated Circuit Design
A Method of Optimization of Clock Gating in Integrated Circuit Designs
Bus Representation for Efficient Physical Synthesis of Integrated Circuit Designs
Method for Recognizing and Verifying Fifo Structures in Integrated Circuit Designs
Methods for Automatically Generating Assertions
Patent:
7,926,020 →
Application:
11/672,919 →
Method for Modeling and Verifying Timing Exceptions
Method for Checking Constraints Equivalence of an Integrated Circuit Design
Method for Computing Power Savings and Determining the Preferred Clock Gating Circuit of an Integrated Circuit Design
Method, System, and Computer Program Product for Generating and Verifying Isolation Logic Modules in Design of Integrated Circuits
Method for Compaction of Timing Exception Paths
Systems and Methods for Generating Predicates and Assertions
Patent:
8,326,778 →
Application:
12/649,144 →
Method and System for Equivalence Checking
Method and System Thereof for Optimization of Power Consumption of Scan Chains of an Integrated Circuit for Test
System and Method for Metastability Verification of Circuits of an Integrated Circuit
Computer-Aided Design System and Methods Thereof for Merging Design Constraint Files Across Operational Modes
Apparatus and Method Thereof for Hybrid Timing Exception Verification of an Integrated Circuit Design
Hierarchical Bottom-Up Clock Domain Crossing Verification
System and Method for Inferring Higher Level Descriptions from Rtl Topology Based on Naming Similarities and Dependency
System and Methods for Inferring Higher Level Descriptions from Rtl Topology Based on Connectivity Propagation
Characterization Based Buffering and Sizing for System Performance Optimization
Method for Generating an Integrated and Unified View of Ip-Cores for Hierarchical Analysis of a System on Chip (Soc) Design
Patent:
8,533,647 →
Application:
13/645,897 →
Systems, Methods, and Media for Assertion-Based Verification of Devices
Patent:
9,135,382 →
Application:
13/672,477 →
Systems and Methods for Generating a Higher Level Description of a Circuit Design Based on Connectivity Strengths
System and Method for Large Multiplexer Identification and Creation in a Design of an Integrated Circuit
Patent:
8,739,087 →
Application:
13/756,083 →
Sequential Clock Gating Using Net Activity and Xor Technique on Semiconductor Designs Including Already Gated Pipeline Design
Patent:
8,656,326 →
Application:
13/766,017 →
Method for Measuring Assertion Density in a System of Verifying Integrated Circuit Design
System and Method for Abstraction of a Circuit Portion of an Integrated Circuit
Patent:
8,656,328 →
Application:
13/791,492 →
System and Method for Strengthening of a Circuit Element to Reduce an Integrated Circuit's Power Consumption
Patent:
8,635,578 →
Application:
13/828,709 →
System and Method for Altering Circuit Design Hierarchy to Optimize Routing and Power Distribution
Method and System Thereof for Optimization of Power Consumption of Scan Chains of an Integrated Circuit for Test
System and Methods for Reasonable Functional Verification of an Integrated Circuit Design
Patent:
8,806,401 →
Application:
13/851,763 →
System and Method for a Hybrid Clock Domain Crossing Verification
System and Method for Filtration of Error Reports Respective of Static and Quasi-Static Signals Within an Integrated Circuit Design
Application:
13/872,303 →
Publication:
US 2014/0282322
System and Method for Metastability Verification of Circuits of an Integrated Circuit
Efficient Apparatus and Method for Analysis of Rtl Structures That Cause Physical Congestion
Patent:
8,745,567 →
Application:
13/952,024 →
Efficient Method to Analyze Rtl Structures That Cause Physical Implementation Issues Based on Rule Checking and Overlap Analysis
Patent:
8,782,582 →
Application:
13/954,097 →
Computer System for Generating an Integrated and Unified View of Ip-Cores for Hierarchical Analysis of a System on Chip (Soc) Design
Method for Creating Physical Connections in 3D Integrated Circuits
Patent:
8,732,647 →
Application:
14/012,734 →
Apparatus and Method Thereof for Hybrid Timing Exception Verification of an Integrated Circuit Design
Method of Global Design Closure at Top Level and Driving of Downstream Implementation Flow
System and Method for Inferring Higher Level Descriptions from Rtl Topology Based on Naming Similarities and Dependency
Sequential Clock Gating Using Net Activity and Xor Technique on Semiconductor Designs Including Already Gated Pipeline Design
Patent:
8,677,295 →
Application:
14/083,109 →
System and Method for Strengthening of a Circuit Element to Reduce an Integrated Circuit's Power Consumption
System and Method for Abstraction of a Circuit Portion of an Integrated Circuit
Application:
14/181,476 →
Publication:
US 2015/0234973
Method and Apparatus Using Formal Methods for Checking Generated-Clock Timing Definitions
Sequential Clock Gating Using Net Activity and Xor Technique on Semiconductor Designs Including Already Gated Pipeline Design
Application:
14/196,089 →
Publication:
US 2015/0143307
System and Method for Reducing Power of a Circuit Using Critical Signal Analysis
Method and System for Selecting Stimulation Signals for Power Estimation
Application:
14/603,188 →
Publication:
US 2016/0217239
Method and System for Checking and Correcting Shoot-Through in Rtl Simulation
Application:
14/716,422 →
Publication:
US 2016/0342727
System and Method for Viewing and Modifying Configurable Rtl Modules
System and Method for Grading and Selecting Simulation Tests Using Property Coverage
Application:
14/745,700 →
Publication:
US 2015/0379186
System and Method for Netlist Clock Domain Crossing Verification
System and Method for Reactive Initialization Based Formal Verification of Electronic Logic Design
System and Method for Managing and Composing Verification Engines
System and Method Using Pass/Fail Test Results to Prioritize Electronic Design Verification Review
Application:
14/812,109 →
Publication:
US 2016/0063162
System and Method for Power Verification Using Efficient Merging of Power State Tables
Piezoelectric Touch-Controlled Faucet
Application:
14/815,305 →
Publication:
US 2016/0032571
System and Method for Filtration of Error Reports Respective of Static and Quasi-Static Signals within an Integrated Circuit Design
Application:
61/786,671 →
System and Methods for Reducing Power of a Circuit Using Critical Signal Analysis
Application:
62/009,275 →
System and Method for grading and selecting Simulation Tests using Property Coverage
Application:
62/019,333 →
System and method for viewing and modifying configurable RTL modules
Application:
62/019,360 →
System and method using pass/fail test results to prioritize electronic design verification review issues
Application:
62/041,661 →
System and method for generating properties to assist emulation debug
Application:
62/072,986 →
System and Method for Netlist Clock Domain Crossing Verification
Application:
62/129,645 →
System and method for power verification using efficient merging of power state tables
Application:
62/140,386 →
System and method for reactive initialization based verification
Application:
62/146,927 →
System and Method for Hierarchical Power Verification
Application:
62/189,453 →
Related Assignments
(22)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Aug 1, 2003
From: KAPOOR, BHANU; CHURIWALA, SANJAY; BANERJEE, JOY
To: ATRENTA, INC.
Reel/Frame 014356/0397 →
Assignment of Assignor's Interest
Oct 30, 2003
From: SARWARY, MOHAMED SHAKER; EZAZI, MOHAMMAD MOVAHED; MURPHY, BERNARD
To: ATRENTA INC.
Reel/Frame 014667/0380 →
Assignment of Assignor's Interest
Sep 21, 2004
From: KAPOOR, BHANU; BAGCHI, DEBABRATA; CHURIWALA, SANJAY
To: ATRENTA, INC.
Reel/Frame 015155/0391 →
Assignment of Assignor's Interest
Oct 15, 2004
From: KAPOOR, BHANU; BAGCHI, DEBABRATA
To: ATRENTA, INC.
Reel/Frame 015250/0734 →
Assignment of Assignor's Interest
Mar 4, 2005
From: MURPHY, BERNARD; PRASOON, PRATYUSH KUMAR; BHATIA, MANISH
To: ATRENTA, INC.
Reel/Frame 016337/0671 →
Security Agreement
Feb 2, 2006
From: ATRENTA, INC.
To: HERCULES TECHNOLOGY GROWTH CAPITAL, INC.
Reel/Frame 017105/0594 →
Assignment of Assignor's Interest
Jul 10, 2006
From: KAPOOR, BHANU; BAGCHI, DEBABRATA; SHARMA, NITIN
To: ATRENTA, INC.
Reel/Frame 017904/0883 →
Security Agreement
Aug 8, 2006
From: ATRENTA, INC.
To: COMERICA BANK
Reel/Frame 018073/0119 →
Assignment of Assignor's Interest
Dec 14, 2006
From: SARWARY, SHAKER; YUAN, JUN; MURPHY, BERNARD; HARI, ASHISH
To: ATRENTA, INC.
Reel/Frame 018763/0716 →
Assignment of Assignor's Interest
May 16, 2007
From: RAHIM, SOLAIMAN; JAIN, MAYANK
To: ATRENTA, INC.
Reel/Frame 019302/0294 →
Assignment of Assignor's Interest
Jul 23, 2007
From: GANGADHARAN, SRIDHAR; GOEL, MANISH; PRASOON, PRATYUSH K.; BHARECH, SURAJ
To: ATRENTA, INC.
Reel/Frame 019585/0076 →
Assignment of Assignor's Interest
Aug 10, 2007
From: ALLEN, DAVID L.
To: ATRENTA, INC.
Reel/Frame 019680/0499 →
Security Agreement
Jul 10, 2008
From: ATRENTA, INC.
To: HERCULES TECHNOLOGY GROWTH CAPITAL, INC.
Reel/Frame 021222/0668 →
Assignment of Assignor's Interest
Oct 1, 2008
From: VARADARAJAN, RAVI
To: ATRENTA, INC.
Reel/Frame 021613/0168 →
Security Agreement
Apr 15, 2009
From: ATRENTA INC.
To: SILICON VALLEY BANK
Reel/Frame 022542/0570 →
Release of Security Interest
Apr 16, 2009
From: COMERICA BANK
To: ATRENTA, INC.
Reel/Frame 022552/0216 →
Release of Security Interest
Apr 17, 2009
From: HERCULES TECHNOLOGY GROWTH CAPITAL, INC.
To: ATRENTA INC.
Reel/Frame 022552/0639 →
Assignment of Assignor's Interest
Mar 15, 2011
From: ZHU, YUNSHAN; LU, YUAN
To: NEXTOP SOFTWARE, INC.
Reel/Frame 025955/0100 →
Release of Security Interest
Sep 1, 2011
From: HERCULES TECHNOLOGY GROWTH CAPITAL, INC.
To: ATRENTA, INC.
Reel/Frame 026846/0954 →
Assignment of Assignor's Interest
Jan 18, 2013
From: NEXTOP SOFTWARE, INC.
To: ATRENTA, INC.
Reel/Frame 029655/0831 →
Release of Security Interest
May 14, 2015
From: HERCULES TECHNOLOGY GROWTH CAPITAL, INC
To: ATRENTA, INC
Reel/Frame 035640/0528 →
Assignment of Assignor's Interest
Sep 25, 2015
From: ATRENTA INC.
To: SYNOPSYS, INC.
Reel/Frame 036687/0290 →