Apparatus and method thereof for hybrid timing exception verification of an integrated circuit design
View Patent ↗Timing Constraints are crucial to meet timing requirements of an Integrated Circuit (IC). Timing exceptions are specified so that certain paths of the design of the IC are not timed as they are not relevant for the speed of the IC. If a path is specified as an exception but it is indeed a timing-relevant path then the design may functionally fail due to timing violations ignored by the timing analysis tools. It is therefore extremely important to ensure that all timing exceptions are correctly specified. The Hybrid Timing Exceptions Verification uses static verification as well as dynamic verification to effectively verify correctness of such timing exceptions. The solution pin-points the errors in the exceptions specification with very low number of false errors that would require significant designer inputs and time to manually waive them.
1. A computerized method for verification of timing exceptions of an integrated circuit (IC) design, the method comprising:
performing by a computing device at least a dynamic verification using a test-bench of the IC design to verify correctness of at least a dynamic timing exception, filtered out from a static verification of at least a static timing exception of the IC design, that is contained in at least a constraints file of the IC design to identify any dynamic timing exception failures; and
correcting any timing exception or design bug respective of an identified dynamic timing exception failure caused by simulation of an assertion for at least one timing exception and updating the IC design and the respective design constraint files respective of the correction.
2. The computerized method of claim 1 , wherein performing by a computing device at least a dynamic verification comprises:
generating by a computing device monitors and assertions for timing exceptions categorized as dynamic timing exceptions.
3. The computerized method of claim 2 , further comprising:
receiving the test bench that contains at least a test vector for the IC design.
4. The computerized method of claim 3 , further comprising:
performing by a computing device a simulation of the IC design using the test bench instrumented with the monitors and assertions.
5. The computerized method of claim 4 , further comprising:
collecting by a computing device errors from the performance of the simulation responsive of the monitors and assertions indicating a failure of at least one of the dynamic timing exceptions.
6. The computerized method of claim 5 , further comprising:
repeating at least once more the method of claim 1 beginning with the receiving the IC's design and the respective design constraint file.
7. The computerized method of claim 1 , further comprising:
generating a coverage report respective of coverage of the dynamic verification.
8. A non-transitory computer readable storage medium storing instructions for enabling a computer to perform the computerized method of claim 1 .
9. A system for verification of timing exceptions of an IC design that performs on the computing device at least the dynamic verification according to the computerized method of claim 1 .
10. The system of claim 9 , wherein the system is a computer aided design (CAD) system.
11. The computerized method of claim 1 , further comprising:
performing by a computing device a static verification of timing exceptions categorized as belonging to at least one of static structural timing exceptions and static formal timing exceptions and generating a report containing errors respective of at least one of static structural timing exception failures and static formal timing exception failures.
12. The computerized method of claim 11 , further comprising:
correcting the timing exceptions responsive to the report respective of at least one static structural timing exception failures and static formal timing exception failures and updating the IC design or the respective design constraints file respective of the corrections to the timing exceptions.