Method for clock synchronization validation in integrated circuit design
View Patent ↗Unsynchronized clock-domain crossings in the design of integrated circuit are detected by searching for clock-crossing domains. For each clock-crossing that does not include an explicit synchronization cell, an analysis determines if the clock is stable crossing the domains.
1. A method for verifying unstable clock-domain crossings in integrated circuit (IC) designs, comprising: identifying candidate unstable clock-domain crossings using a clock synchronization analysis tool; performing a validity check for each of the candidate unstable clock-domain crossings; and eliminating a candidate unstable clock-domain crossing when the validity check does not indicate an unstable clock-domain crossing;
wherein the validity check comprises making a stability determination for each of the candidate unstable clock-domain crossings, and
wherein the stability determination is based on satisfaction of a stability function.
2. The method of claim 1 , wherein the unstable clock-domain crossing is indicated when a time frame destabilizes a clock-domain crossing.
3. The method of claim 2 , wherein the time frame comprises a set of clock signals, and wherein each of the clock signals clocks a different register belonging to the candidate unstable clock-domain crossing.
4. The method of claim 1 , wherein the clock synchronization analysis tool performs a structural analysis.
5. The method of claim 1 , executed on at least one of: computer aided design (CAD) system, a CAD program, a clock synchronization analysis tool.
6. A method for verifying unstable clock-domain crossings in integrated circuit (IC) designs, comprising: identifying candidate unstable clock-domain crossings using a clock synchronization analysis tool; performing a validity check for each of the candidate unstable clock-domain crossings; and eliminating a candidate unstable clock-domain crossing when the validity check does not indicate an unstable clock-domain crossing;
wherein the validity check comprises making a stability determination for each of the candidate unstable clock-domain crossings, and
wherein the stability determination is performed using at least one of model checking and bounded model checking (BMC).
7. The method of claim 6 , wherein the BMC is performed using at least a Boolean satisfiability (SAT) solver.
8. A computer program product, including a computer readable medium with computer instructions, for use by a computer to perform operations for verifying unstable clock-domain crossings in integrated circuit (IC) designs, comprising: identifying candidate unstable clock-domain crossings using a clock synchronization analysis tool; performing a validity check for each of the candidate unstable clock-domain crossings, and eliminating a candidate unstable clock-domain crossing when the validity check does not indicate an unstable clock-domain crossing;
wherein the validity check comprises making a stability determination for each of the candidate unstable clock-domain crossings, and
wherein the stability determination is based on satisfaction of a stability function.
9. The computer program product of claim 8 , wherein the unstable clock-domain crossing is indicated when a time frame destabilizes a clock-domain crossing.
10. The computer program product of claim 9 , wherein the time frame comprises a set of clock signals, and wherein each of the clock signals clocks a different register belonging to the candidate unstable clock-domain crossing.
11. The computer program product of claim 8 , wherein the clock synchronization analysis tool performs a structural analysis.
12. The computer program product of claim 8 , executed on at least one of: computer aided design (CAD) system, a CAD program, a clock synchronization analysis tool.
13. A computer program product, including a computer readable medium with computer instructions, for use by a computer to perform operations for verifying unstable clock-domain crossings in integrated circuit (IC) designs, comprising: identifying candidate unstable clock-domain crossings using a clock synchronization analysis tool; performing a validity check for each of the candidate unstable clock-domain crossings; and eliminating a candidate unstable clock-domain crossing when the validity check does not indicate an unstable clock-domain crossing;
wherein the validity check comprises making a stability determination for each of the candidate unstable clock-domain crossings, and
wherein the stability determination is performed using at least one of model checking and bounded model checking (BMC).
14. The computer program product of claim 13 , wherein the BMC is performed using at least a Boolean satisfiability (SAT) solver.
15. A computer system, adapted to implement a method for detecting unstable clock-domain crossings in a design of an integrated circuit (IC), comprising: a processor; and a memory including software instructions adapted to enable the computer system to perform the operations of: identifying candidate unstable clock-domain crossings using a clock synchronization analysis tool; performing a validity check for each of the candidate unstable clock-domain crossings; and eliminating a candidate unstable clock-domain crossing when the validity check does not indicate an unstable clock-domain crossing;
wherein the validity check comprises making a stability determination for each of the candidate unstable clock-domain crossings; and
wherein the stability determination is based on satisfaction of a stability function.
16. The system of claim 15 , wherein the unstable clock-domain crossing is indicated when a time frame destabilizes a candidate clock-domain crossing.
17. The system of claim 16 , wherein the time frame comprises a set of clock signals, and wherein each of the clock signals clocks a different register belonging to the candidate unstable clock-domain crossing.
18. The system of claim 15 , wherein the clock synchronization analysis tool performs a structural analysis.
19. The system of claim 15 , executed on at least one of: computer aided design (CAD) system, a CAD program, a clock synchronization analysis tool.
20. A computer system, adapted to implement a method for detecting unstable clock-domain crossings in a design of an integrated circuit (IC), comprising: a processor; and a memory including software instructions adapted to enable the computer system to perform the operations of: identifying candidate unstable clock-domain crossings using a clock synchronization analysis tool; performing a validity check for each of the candidate unstable clock-domain crossings; and eliminating a candidate unstable clock-domain crossing when the validity check does not indicate an unstable clock-domain crossing;
wherein the validity check comprises making a respective stability determination for the candidate unstable clock-domain crossings; and
wherein the stability determination is performed using at least one of model checking and bounded model checking (BMC).
21. The system of claim 20 , wherein the BMC is performed using at least a Boolean satisfiability (SAT) solver.