IP Library › Assignment 035640/0528
Patent Assignment
Reel/Frame 035640/0528

Release of Security Interest

Recorded: 2015-05-14 Pages: 3
Assignor
Assignee
ATRENTA, INC
2077 GATEWAY PL, STE.300, SAN JOSE, CALIFORNIA, 95110
Covered Properties (2)
Method for Clock Synchronization Validation in Integrated Circuit Design
Patent: 7,506,292 →
Application: 11/276,819 →
Publication: US 2006/0150043
Method, System, and Computer Program Product for Generating and Verifying Isolation Logic Modules in Design of Integrated Circuits
Patent: 7,712,061 →
Application: 11/959,427 →
Publication: US 2008/0098338
Related Assignments (5)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Agreement Jul 10, 2008
From: ATRENTA, INC.
To: HERCULES TECHNOLOGY GROWTH CAPITAL, INC.
Reel/Frame 021222/0668 →
Security Agreement Apr 15, 2009
From: ATRENTA INC.
To: SILICON VALLEY BANK
Reel/Frame 022542/0570 →
Release of Security Interest Sep 10, 2015
From: SILICON VALLEY BANK
To: ATRENTA INC.
Reel/Frame 036584/0644 →
Assignment of Assignor's Interest Sep 25, 2015
From: ATRENTA INC.
To: SYNOPSYS, INC.
Reel/Frame 036687/0290 →
Assignment of Assignor's Interest Jan 15, 2016
From: KAPOOR, BHANU; BAGCHI, DEBABRATA; CHURIWALA, SANJAY
To: ATRENTA, INC.
Reel/Frame 037501/0035 →