Hierarchical bottom-up clock domain crossing verification
View Patent ↗Clock-domain crossing (CDC) verification for system on chip (SoC) integrated circuits (IC) can be time consuming and complex, especially as the size of the SoC and the complexity of the modules of which it comprises increase. A bottom-up verification process includes the replacement of a CDC verified module by an abstracted model of the module with constraints defined on the boundaries of the module. Performing the process in a hierarchic manner from bottom upwards allows for faster verification of modules higher in the hierarchy as at least portions thereof are replaced with the abstracted modules.
1. A method for clock-domain crossing (CDC) verification of a model of an integrated circuit (IC) comprising a plurality of modules, the method comprising:
identifying a module from among the plurality of modules that has not been previously abstracted or that has not changed since a previous abstraction, the module having an input and an output;
performing a CDC verification on the module in a bottom-up fashion by a computer processor device;
replacing the module with a corresponding abstraction module that correctly identifies a corresponding clock-domain for each of the input and the output, the replacing performed in response to the module successfully passing the respective CDC verification;
repeating the identifying, performing, and replacing for each of the remaining modules from among the plurality of modules; and
storing an updated model of the IC comprising at least a replaced module in storage.
2. The method of claim 1 , wherein the abstraction model includes an assumption for the input of the module and a constraint for an output port of the output of the module.
3. The method of claim 2 , further comprising:
verifying the assumption when validating a higher level module that includes the abstracted module.
4. The method of claim 2 , wherein the constraint comprises at least one of: module name, port name, clock domain, name of at least one of synchronizers, flip-flops (FFs), and latches.
5. The method of claim 4 , wherein the constraint is an indication that there is a synchronizer within the clock domain of the output port.
6. The method of claim 5 , wherein the indication further comprises at least one of: a name of a clock that is a source of the synchronizer, a name of a clock that is a destination of the synchronizer, an indication of a delay in the synchronizer for metastability to settle, an indication whether the synchronizer drives the output port with or without latches of flip-flops (FFs) in a path to the output port, an indication whether the synchronizer is active and can synchronize a crossing, and an indication whether the synchronizer is inactive not being able to synchronize a clock-domain crossing.
7. The method of claim 4 , wherein the constraint is an indication of an input port that has a structural path to the output port.
8. The method of claim 2 , wherein the constraint comprises at least an indication of combinational logic within the module with respect to the output port.
9. The method of claim 8 , wherein the indication is one of: combinational logic exists, combinational logic does not exist, combinational logic is irrelevant.
10. A computer program product containing a plurality of instructions embedded in a non-transitory computer readable medium that when executed by a computing device causes the computing device to execute a method for clock-domain crossing (CDC) verification of a model of an integrated circuit (IC) comprising a plurality of modules, the method comprising:
identifying a module from among the plurality of modules that has not been previously abstracted or that has not changed since a previous abstraction, the module having an input and an output;
performing a CDC verification on the module in a bottom-up fashion;
replacing the module with a corresponding abstraction module that correctly identifies a corresponding clock-domain for each of the input and the output, the replacing performed in response to the module successfully passing the respective CDC verification;
repeating the identifying, performing, and replacing for each of the remaining modules from among the plurality of modules; and
storing an updated model of the IC comprising at least a replaced module in storage.
11. A system comprising a processing unit and a memory communicably coupled to the processing unit, the memory storing a design file for an integrated circuit and instructions for enabling the processing unit to perform a clock-domain crossing (CDC) verification of a model of an integrated circuit (IC) comprising a plurality of modules, wherein the processing unit:
identifies a module from among the plurality of modules that has not been previously abstracted or that has not changed since a previous abstraction, the module having an input and an output;
performs a CDC verification on the module in a bottom-up fashion;
replaces the module with a corresponding abstraction module that correctly identifies a corresponding clock-domain for each of the input and the output, the replacing performed in response to the module successfully passing the respective CDC verification;
repeats the identifying, performing, and replacing for each of the remaining modules from among the plurality of modules; and
stores an updated model of the IC comprising at least a replaced module in the memory.
12. The system of claim 11 , wherein the system is a computer aided design (CAD) system.