IP Library › Assignment 017105/0594
Patent Assignment
Reel/Frame 017105/0594

Security Agreement

Recorded: 2006-02-02 Pages: 9
Assignor
ATRENTA, INC.
Executed: 2005-12-29
Assignee
HERCULES TECHNOLOGY GROWTH CAPITAL, INC.
525 UNIVERSITY AVENUE, SUITE 700, PALO ALTO, CALIFORNIA, 94301
Covered Properties (11)
Apparatus and Method for Handling of Multi-Level Circuit Design Data
Patent: 6,993,733 →
Application: 10/118,242 →
Publication: US 2003/0192023
Method for Detecting Bus Contention from Rtl Description
Patent: 7,277,840 →
Application: 10/172,996 →
Publication: US 2003/0233504
Method for Determining Fault Coverage from Rtl Description
Patent: 6,876,934 →
Application: 10/217,535 →
Publication: US 2004/0034495
Identification and Implementation of Clock Gating in the Design of Integrated Circuits
Patent: 7,076,748 →
Application: 10/631,755 →
Publication: US 2005/0028118
Method for Clock Synchronization Validation in Integrated Circuit Design
Patent: 7,073,146 →
Application: 10/695,803 →
Publication: US 2005/0097484
A Method, System, and Computer Program Product for Generating and Verifying Isolation Logic Modules in Design of Integrated Circuits
Patent: 7,349,835 →
Application: 10/711,493 →
Publication: US 2006/0064293
A Method, System, and Computer Program Product for Automatic Insertion and Correctness Verification of Level Shifters in Integrated Circuits with Multiple Voltage Domains
Patent: 7,152,216 →
Application: 10/711,971 →
Publication: US 2006/0085770
Pattern Recognition in an Integrated Circuit Design
Patent: 7,216,321 →
Application: 10/783,091 →
Publication: US 2005/0108675
A Method for Automatic Recognition of Handshake Data Exchange at Clock-Domain Crossing in Integrated Circuit Design
Application: 10/906,571 →
Publication: US 2006/0190754
Chip Development System Enabled for the Handling of Multi-Level Circuit Design Data
Patent: 7,421,670 →
Application: 11/260,225 →
Publication: US 2006/0048083
Bus representation for efficient physical synthesis of integrated circuit designs
Application: 60/689,545 →
Related Assignments (13)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Aug 1, 2003
From: KAPOOR, BHANU; CHURIWALA, SANJAY; BANERJEE, JOY
To: ATRENTA, INC.
Reel/Frame 014356/0397 →
Assignment of Assignor's Interest Oct 30, 2003
From: SARWARY, MOHAMED SHAKER; EZAZI, MOHAMMAD MOVAHED; MURPHY, BERNARD
To: ATRENTA INC.
Reel/Frame 014667/0380 →
Assignment of Assignor's Interest Sep 21, 2004
From: KAPOOR, BHANU; BAGCHI, DEBABRATA; CHURIWALA, SANJAY
To: ATRENTA, INC.
Reel/Frame 015155/0391 →
Assignment of Assignor's Interest Oct 15, 2004
From: KAPOOR, BHANU; BAGCHI, DEBABRATA
To: ATRENTA, INC.
Reel/Frame 015250/0734 →
Assignment of Assignor's Interest Feb 24, 2005
From: DARGELAS, ALAIN; MAL JAIN, PARAS; HARI, ASHISH; MURPHY, BERNARD
To: ATRENTA, INC.
Reel/Frame 015704/0503 →
Assignment of Assignor's Interest Mar 4, 2005
From: MURPHY, BERNARD; PRASOON, PRATYUSH KUMAR; BHATIA, MANISH
To: ATRENTA, INC.
Reel/Frame 016337/0671 →
Security Agreement Aug 8, 2006
From: ATRENTA, INC.
To: COMERICA BANK
Reel/Frame 018073/0119 →
Security Agreement Apr 15, 2009
From: ATRENTA INC.
To: SILICON VALLEY BANK
Reel/Frame 022542/0570 →
Release of Security Interest Apr 16, 2009
From: COMERICA BANK
To: ATRENTA, INC.
Reel/Frame 022552/0216 →
Release of Security Interest Apr 17, 2009
From: HERCULES TECHNOLOGY GROWTH CAPITAL, INC.
To: ATRENTA INC.
Reel/Frame 022552/0639 →
Release of Security Interest Sep 1, 2011
From: HERCULES TECHNOLOGY GROWTH CAPITAL, INC.
To: ATRENTA, INC.
Reel/Frame 026846/0954 →
Release of Security Interest Sep 10, 2015
From: SILICON VALLEY BANK
To: ATRENTA INC.
Reel/Frame 036584/0644 →
Assignment of Assignor's Interest Sep 25, 2015
From: ATRENTA INC.
To: SYNOPSYS, INC.
Reel/Frame 036687/0290 →