Patent Assignment
Reel/Frame 022552/0216
Release of Security Interest
Recorded: 2009-04-16
Pages: 4
Assignor
COMERICA BANK
Executed: 2009-04-15
Assignee
ATRENTA, INC.
2077 GATEWAY PLACE, SUITE 300, SAN JOSE, CALIFORNIA, 95110
Covered Properties
(6)
Apparatus and Method for Handling of Multi-Level Circuit Design Data
Method for Detecting Bus Contention from Rtl Description
Method for Determining Fault Coverage from Rtl Description
Identification and Implementation of Clock Gating in the Design of Integrated Circuits
Method for Clock Synchronization Validation in Integrated Circuit Design
Pattern Recognition in an Integrated Circuit Design
Related Assignments
(9)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Aug 1, 2003
From: KAPOOR, BHANU; CHURIWALA, SANJAY; BANERJEE, JOY
To: ATRENTA, INC.
Reel/Frame 014356/0397 →
Assignment of Assignor's Interest
Oct 30, 2003
From: SARWARY, MOHAMED SHAKER; EZAZI, MOHAMMAD MOVAHED; MURPHY, BERNARD
To: ATRENTA INC.
Reel/Frame 014667/0380 →
Assignment of Assignor's Interest
Mar 4, 2005
From: MURPHY, BERNARD; PRASOON, PRATYUSH KUMAR; BHATIA, MANISH
To: ATRENTA, INC.
Reel/Frame 016337/0671 →
Security Agreement
Feb 2, 2006
From: ATRENTA, INC.
To: HERCULES TECHNOLOGY GROWTH CAPITAL, INC.
Reel/Frame 017105/0594 →
Security Agreement
Aug 8, 2006
From: ATRENTA, INC.
To: COMERICA BANK
Reel/Frame 018073/0119 →
Security Agreement
Apr 15, 2009
From: ATRENTA INC.
To: SILICON VALLEY BANK
Reel/Frame 022542/0570 →
Release of Security Interest
Apr 17, 2009
From: HERCULES TECHNOLOGY GROWTH CAPITAL, INC.
To: ATRENTA INC.
Reel/Frame 022552/0639 →
Release of Security Interest
Sep 10, 2015
From: SILICON VALLEY BANK
To: ATRENTA INC.
Reel/Frame 036584/0644 →
Assignment of Assignor's Interest
Sep 25, 2015
From: ATRENTA INC.
To: SYNOPSYS, INC.
Reel/Frame 036687/0290 →