System and method for reducing power of a circuit using critical signal analysis
View Patent ↗A system and methods provide for an analysis of at least a portion of an integrated circuit (IC) that comprises a plurality of modules, for the purpose of identifying signals that can be indicative of the activity of the modules. By analyzing the activity of these signal immediately before and immediately after each module going from non-idle to idle and from idle to non-idle respectively, it is possible to determine which signals provide an indication that the module should be shut down. If the module can be shut down in idle state, then these input signals may be used as control signals for this purpose. By reporting to a designer the role of such signals a simple design change for detecting the activity and controlling the module, can save on power consumption, in ways not previously detected by the designer.
1. A computerized method, implemented in a programmable system having at least a processing unit and a storage, for determination of signals to be used for achieving power consumption reduction of an integrated circuit (IC), the method comprising:
receiving from storage by the programmable system a description of at least a portion of an IC, the received circuit description comprising a plurality of circuit modules (CMs);
performing a power consumption simulation of the IC from the received description, by execution of instructions on a processing unit of the programmable system, so as to generate a power consumption time series for each CM;
performing an analysis of the power consumption time series respective of each CM, by execution of instructions on the processing unit, so as to identify existence of any one or more idle periods for each CM;
selecting, by execution of instructions on the processing unit, any CM having at least one idle period that is above a predetermined threshold value; and
performing an analysis on all the input signals of each selected CM, by execution of instructions on the processing unit respective of each selected CM, so as to determine at least one input signal of all selected CM's input signals that are correlated to transitions of such selected CM between its idle and non-idle states.
2. The computerized method of claim 1 , wherein idle periods for each CM are determined by a CM being idle for at least some specified period of time.
3. The computerized method of claim 1 , further comprises:
saving in the storage the determined at least one input signal for each CM.
4. The computerized method of claim 1 , further comprises:
displaying on a display the determined at least one input signal for each CM.
5. The computerized method of claim 1 , wherein the selecting a CM further comprises:
determining the existence of period of a first point in time of an activity decrease above a first predetermined threshold; and
determining the existence of a second point in time subsequent to the first point in time of an activity increase to above a second predetermined threshold.
6. The computerized method of claim 1 , wherein the correlation to transitions of a selected CM between idle and non-idle states further comprises:
determining an activity of at least one input in a period of time immediately preceding a transition between idle and non-idle states.
7. The computerized method of claim 6 , wherein the period of time immediately preceding a transition between idle and non-idle states is a programmable value of the computerized method.
8. The computerized method of claim 1 , further comprising:
receiving a specified peak activity threshold value;
identifying whether the peak activity threshold value is exceeded at any time period of the power consumption simulation.
9. The computerized method of claim 8 , further comprises:
reporting each time period where the at least one circuit of the IC exceeds the peak power threshold value.
10. The computerized method of claim 1 , wherein the selecting a CM further comprises:
generating for each flip-flop of the CM an activity signal being an exclusive OR function (XOR) of an input and output respective of that flip-flop;
generating a CM activity signal that is a NOR of the activity signals of the CM; and
determining any period where the CM activity signal is idle.
11. The computerized method of claim 1 , wherein partitions of the received circuit description into a plurality of circuit modules (CMs) groups flip-flops sharing a same clock into the same CM.
12. A computer aided design (CAD) system configured to execute the method of claim 1 .
13. A system for determining candidate signals to be used to control power consumption of an integrated circuit (IC) comprising:
at least one processing unit; and
a memory connected to the at least one processing unit, the memory containing instructions therein that when executed by the at least one processing unit configure the system to: receive a description of at least a portion of the IC, the received circuit description comprising a plurality of circuit modules (CMs); perform a power consumption simulation of the IC from the received description so as to generate a power consumption time series for each CM; perform an analysis of the power consumption time series so as to identify existence of any one or more idle periods for each CM; select any CM having at least one idle period that is above a predetermined threshold value; and perform an analysis on all the input signals of each selected CM so as to determine at least one input signal of all selected CM's input signals that are correlated to transitions of such selected CM between its idle and non-idle states.
14. The system of claim 13 , wherein idle periods for each CM are determined by a CM being idle for at least some specified period of time.
15. The system of claim 13 , wherein the memory further contains instructions that when executed by the at least one processing unit configure the system to: save in the memory for future use the determined at least one input signal for each CM.
16. The system of claim 13 , wherein the memory further contains instructions that when executed by the at least one processing unit configure the system to: display on a display of the system the determined at least one input signal for each CM.
17. The system of claim 13 , wherein selection of a CM further comprises instructions that when executed by the at least one processing unit configure the system to:
determine the existence of period of a first point in time of a power consumption decrease above a first predetermined threshold; and
determine the existence of a second point in time subsequent to the first point in time of a power consumption increase to above a second predetermined threshold.
18. The system of claim 13 , wherein the correlation to transitions of a selected CM between idle and non-idle states further comprises instructions that when executed by the at least one processing unit configure the system to: determine an activity of at least one input in a period of time immediately preceding a transition between idle and non-idle states.
19. The system of claim 18 , wherein the period of time immediately preceding a transition between idle and non-idle states is a programmable value of the computerized method.
20. The system of claim 13 , wherein the memory further contains instructions that when executed by the at least one processing unit configure the system to:
receive a specified peak activity threshold value; and
identify whether the peak activity threshold value is exceeded at any time period of the power consumption simulation.
21. The system of claim 20 , wherein the memory further contains instructions that when executed by the at least one processing unit configure the system to: report each time period where the at least one circuit of the IC exceeds the peak power threshold value.
22. The system of claim 13 , wherein, when selecting a CM, the memory further contains instructions that when executed by the at least one processing unit configure the system to:
generate for each flip-flop of the CM an activity signal being an exclusive OR function (XOR) of an input and output respective of that flip-flop;
generate a CM activity signal that is a NOR of the activity signals of the CM; and
determine any period where the CM activity signal is idle.
23. The system of claim 13 , wherein the received circuit description are partitioned into the plurality of circuit modules (CMs) such that flip-flops sharing a same clock are contained within the same CM.
24. The system of claim 13 , wherein the system is a computer aided design (CAD) system for design of integrated circuits.