Method of optimization of clock gating in integrated circuit designs
View Patent ↗A method for optimization of clock gating in integrated circuit (IC) design. Clock gating techniques are very useful in reducing the electrical power consumed by an IC. A general method for identifying registers that are candidates for clock gating is presented. Furthermore, a determination is made regarding which of the candidate registers to clock gate in order to achieve optimal power and IC area savings. The determination is based on switching activity of the candidate registers.
1. An integrated circuit (IC) design method for reducing IC power consumption and IC area by the efficient implementation of register clock gating in an IC design, comprising:
identifying candidate registers of the IC design to be clock gated;
from the candidate registers, determining optimal registers to be clock gated to achieve optimal power and IC area savings;
clock gating the optimal registers: and
storing the register clock gated IC design in a computer readable storage device wherein determining said optimal registers further comprising: computing switching activity of each candidate register; grouping registers having a common clock signal; and calculating gating effectiveness for each group of registers with a common clock signal.
2. The method of claim 1 , wherein the register comprises at least one of: a logic flip-flop, a memory cell, and combinational logic loops that form a de-facto memory.
3. The method of claim 1 , wherein said candidate register comprises at least one of: a register having a feedback loop, and a register with a fanout higher than a predetermined threshold.
4. The method of claim 3 , wherein said feedback loop excludes combinational logic elements.
5. The method of claim 1 , wherein said switching activity comprises: activity of a clock signal, a probability of an enable signal, and a size of the candidate register.
6. The method of claim 5 , wherein said switching activity is computed using at least one of statistical algorithms, simulation-based algorithms, and a combination thereof.
7. The method of claim 5 , wherein computing said switching activity further comprising:
normalizing the activity of clock signals.
8. The method of claim 1 , wherein said gating effectiveness is a function of: the number of registers in a group, activity of the common clock, and probability of an enable signal.
9. The method of claim 8 , wherein groups of registers are sorted according to their computed gating effectiveness.
10. The method of claim 9 , wherein registers having gating effectiveness value above a predefined threshold are optimal registers.
11. The method of claim 1 , wherein gating said optimal register further comprises:
determining an output function of the candidate register;
determining one gating condition for the candidate register;
determining at least one hold expression for the candidate register; and
based on the result of the determining of the output function, the gating condition, and the hold expression, clock gating the candidate register.
12. A computer program product for enabling a computer system to perform operations of an integrated circuit (IC) design method, for reducing IC power consumption and IC area by the efficient implementation of register clock gating in an IC design, the computer program product comprising:
a computer readable storage device having computer instructions for performing the operations of the IC design method, the operations comprising:
identifying candidate registers of the IC design to be clock gated;
from the candidate registers, determining optimal registers to be clock gated to achieve optimal power and IC area savings;
clock gating the optimal registers; and
storing the register clock sated IC design in a computer readable storage device wherein determining said optimal registers further comprising: computing switching activity of each candidate register; grouping registers having a common clock signal; and calculating gating effectiveness for each group of registers with a common clock signal.
13. The computer program product of claim 12 , wherein the register comprises at least one of: a logic flip-flop, a memory cell, and combinational logic loops that form a de-facto memory.
14. The computer program product of claim 12 , wherein said candidate register comprises at least one of: a register having a feedback loop, and a register with a fanout higher than a predetermined threshold.
15. The computer program product of claim 14 , wherein said feedback loop excludes combinational logic elements.
16. The computer program product of claim 12 , wherein said switching activity comprises: activity of a clock signal, a probability of an enable signal, and a size of the candidate register.
17. The computer program product of claim 16 , wherein said switching activity is computed using at least one of statistical algorithms, simulation-based algorithms, and a combination thereof.
18. The computer program product of claim 16 , wherein computing said switching activity further comprising:
normalizing the activity of clock signals.
19. The computer program product of claim 12 , wherein said gating effectiveness is a function of: the number of registers in a group, activity of the common clock, and probability of an enable signal.
20. The computer program product of claim 19 , wherein groups of registers are sorted according to their computed gating effectiveness.
21. The computer program product of claim 20 , wherein registers having gating effectiveness value above a predefined threshold are optimal registers.
22. The computer program product of claim 12 , wherein gating said optimal register further comprises:
determining an output function of the candidate register;
determining one gating condition for the candidate register;
determining at least one hold expression for the candidate register; and
based on the result of the determining of the output function, the gating condition, and the hold expression, clock gating the candidate register.
23. A computer system for performing an integrated circuit (IC) design method, for reducing IC power consumption and IC area by the efficient implementation of register clock gating in an IC design, the computer system having a processor and a memory under control of the processor, the memory including software instructions for performing operations comprising:
identifying candidate registers of the IC design to be clock gated;
from the candidate registers, determining optimal registers to be clock gated to achieve optimal power and IC area savings; and
clock gating the optimal registers; and
storing the register clock gated IC design in a computer readable storage device wherein determining said optimal registers further comprising: computing switching activity of each candidate register; grouping registers having a common clock signal; and calculating gating effectiveness for each group of registers with a common clock signal.
24. The computer system of claim 23 , wherein the register comprises at least one of: a logic flip-flop, a memory cell, and combinational logic loops that form a de-facto memory.
25. The computer system of claim 24 , wherein said candidate register comprises at least one of: a register having a feedback loop, and a register with a fanout higher than a predetermined threshold.
26. The computer system of claim 25 , wherein said feedback loop excludes combinational logic elements.
27. The computer system of claim 23 , wherein said switching activity comprises: activity of a clock signal, a probability of an enable signal, and a size of the candidate register.
28. The computer system of claim 27 , wherein said switching activity is computed using at least one of statistical algorithms, simulation-based algorithms, and a combination thereof.
29. The computer system of claim 27 , wherein computing said switching activity further comprising:
normalizing the activity of clock signals.
30. The computer system of claim 23 , wherein said gating effectiveness is a function of: the number of registers in a group, activity of the common clock, and probability of an enable signal.
31. The computer system of claim 30 , wherein groups of registers are sorted according to their computed gating effectiveness.
32. The computer system of claim 31 , wherein registers having gating effectiveness value above a predefined threshold are optimal registers.
33. The computer system of claim 23 , wherein gating said optimal register further comprises:
determining an output function of the candidate register;
determining one gating condition for the candidate register;
determining at least one hold expression for the candidate register; and
based on the result of the determining of the output function, the gating condition, and the hold expression, clock gating the candidate register.