Apparatus and method thereof for hybrid timing exception verification of an integrated circuit design
View Patent ↗Timing Constraints are crucial to meet timing requirements of an Integrated Circuit (IC). Timing exceptions are specified so that certain paths of the design of the IC are not timed as they are not relevant for the speed of the IC. If a path is specified as an exception but it is indeed a timing-relevant path then the design may functionally fail due to timing violations ignored by the timing analysis tools. It is therefore extremely important to ensure that all timing exceptions are correctly specified. The Hybrid Timing Exceptions Verification uses static verification as well as dynamic verification to effectively verify correctness of such timing exceptions. The solution pin-points the errors in the exceptions specification with very low number of false errors that would require significant designer inputs and time to manually waive them.
1. A computerized method for verification of timing exceptions of an integrated circuit (IC) design, the method comprising:
receiving the IC's design and a respective design constraints file including timing exceptions for the IC;
analyzing by a computing device the timing exceptions to categorize each of the timing exceptions as belonging to at least one of static structural timing exception, static formal timing exception, and dynamic timing exception;
running static formal verification of the timing exceptions categorized as static formal timing exceptions and/or static structural timing exception;
generating by a computing device a report respective of the static formal verification containing errors respective of the static formal timing exception failures and the static structural timing exception failures;
causing at least a correction of at least one of the failed formal timing exception and structural timing exception;
updating the IC design or the respective design constraints file respective of the at least a correction;
generating by a computing device monitors or assertions for timing exceptions categorized as dynamic timing exceptions;
receiving a test bench that contains at least a test vector for the IC design;
performing by a computing device a simulation of the IC design using the test bench instrumented with the monitors or assertions; and
collecting by a computing device errors from the performance of the simulation responsive of the monitors or assertions indicating a failure of at least one of the dynamic timing exceptions.
2. The method of claim 1 , further comprising:
causing a modification of the at least one failed dynamic timing exception; updating the IC design and the respective design constraints file respective of the modification; and repeating at least once more the method of claim 1 beginning with the receiving the IC's design and the respective design constraint file.
3. The method of claim 1 , further comprising:
generating a coverage report indicating at least one of coverage of static verification and coverage of dynamic verification.
4. A non-transitory computer readable storage medium storing instructions for enabling a computer to verify timing exceptions of an integrated circuit (IC) design, the instructions enabling the computer to:
receive the IC's design and a respective design constraints file including timing exceptions for the IC;
analyze the timing exceptions to categorize each of the timing exceptions as belonging to at least one of static structural timing exception, static formal timing exception, and dynamic timing exception;
perform static formal verification of the timing exceptions categorized as static formal timing exceptions and/or static structural timing exception;
generate a report respective of the static formal verification containing errors respective of the static formal timing exception failures and the static structural timing exception failures;
cause at least a correction of at least one of the failed formal timing exception and structural timing exception;
update the IC design or the respective design constraints file respective of the at least a correction;
generate monitors or assertions for timing exceptions categorized as dynamic timing exceptions;
receive a test bench that contains at least a test vector for the IC design;
perform a simulation of the IC design using the test bench instrumented with the monitors or assertions; and
collect errors from the performance of the simulation responsive of the monitors or assertions indicating a failure of at least one of the dynamic timing exceptions.
5. A system for performing a hybrid timing exception verification comprising:
a processor,
a memory, and
data storage,
wherein:
the data storage stores:
an integrated circuit (IC) design file,
a constraints file, the constraint file including timing exceptions for the IC, and
a test bench containing at least a test vector for the IC,
wherein:
the processor performs static verification of the IC design file and a first timing exception from the respective constraints file and thereafter performs a dynamic verification of the IC design respective of at least a second timing exception from the respective constraints file; and
wherein performing static verification and performing dynamic verification includes:
receiving the IC's design and the respective design constraints file including timing exceptions for the IC;
analyzing the timing exceptions to categorize each of the timing exceptions as belonging to at least one of static structural timing exception, static formal timing exception, and dynamic timing exception;
running static formal verification of the timing exceptions categorized as static formal timing exceptions and/or static structural timing exception;
generating a report respective of the static formal verification containing errors respective of the static formal timing exception failures and the static structural timing exception failures;
causing at least a correction of at least one of the failed formal timing exception and structural timing exception;
updating the IC design or the respective design constraints file respective of the at least a correction;
generating monitors or assertions for timing exceptions categorized as dynamic timing exceptions;
receiving a test bench for the IC design;
performing a simulation of the IC design using the test bench instrumented with the monitors or assertions; and
collecting errors from the performance of the simulation responsive of the monitors or assertions indicating a failure of at least one of the dynamic timing exceptions.
6. The system of claim 5 , wherein the processor generates a coverage report indicating at least one of coverage of static verification and coverage of dynamic verification.