Methods, apparatus, and systems for determining 1T state metric differences in an nT implementation of a viterbi decoder
Methods, apparatus, and systems for generating bit-wise reliability information using a soft output Viterbi algorithm (“SOVA”) in an nT Viterbi decoder implementation devoid of 1T metric information. At each nT clock pulse 1T equivalent metric values are determined from the current nT metric information. 1T equivalent metric information is determined as values that sum to the corresponding nT metric information. Subtraction is then used to determine state metric difference information from the 1T equivalent metric values. The state metric difference information may then be used to estimate log likelihood ratio information for use in the SOVA algorithm to determine bit-wise reliability information.
1. A method operable in a circuit associated with an nT Viterbi algorithm decoder circuit having associated nT branch metric information for soft output reliability determination where n is an integer greater than 1, the method comprising:
determining 1T equivalent branch metric information derived from the nT branch metric information; and
using the 1T equivalent branch metric information to determine bit-wise soft output reliability information of the nT Viterbi decoder.
2. The method of claim 1
wherein the step of determining 1T equivalent branch metric information further comprises:
determining 1T equivalent branch metric information for each nT branch metric value of the nT branch metric information as multiple 1T branch metric values that sum to a corresponding said each nT branch metric value.
3. The method of claim 2 wherein the step of determining 1T equivalent branch metric information for each nT branch metric value further comprises:
determining 1T equivalent branch metric information for each nT branch metric value of the nT branch metric information as n 1T branch metric values that sum to a corresponding said each nT branch metric value.
4. The method of claim 1
wherein the nT Viterbi algorithm decoder is a 2T Viterbi algorithm decoder,
wherein the nT branch metric information is 2T branch metric information, and
wherein the step of determining 1T equivalent branch metric information further comprises:
determining 1T equivalent branch metric information for each 2T branch metric value of the 2T branch metric information as two 1T branch metric values that sum to a corresponding said each 2T branch metric value.
5. The method of claim 1
wherein the step of using the 1T equivalent branch metric information further comprises:
using the 1T equivalent branch metric information to determine 1T state metric difference information; and
using the 1T state metric difference information to determine the soft output bit-wise reliability information of the nT Viterbi algorithm decoder.
6. A method operable in a circuit associated with an nT Viterbi decoder circuit wherein n is an integer greater than 1, the method comprising:
receiving a sequence of events representing an encoded symbol wherein each event represents n bits of the encoded symbol; and
operating a soft output Viterbi algorithm state machine in the decoder to decode the encoded symbol from the received sequence of events to generate a corresponding decoded symbol and to generate a bit-wise reliability value for each bit of the decoded symbol, wherein the step of operating the soft output Viterbi algorithm state machine further comprises:
generating said bit-wise reliability values for the decoded symbol by utilizing 1T equivalent branch metric information derived from nT branch metric information associated with the soft output Viterbi algorithm state machine.
7. The method of claim 6
wherein the step of generating said bit-wise reliability value further comprises:
generating n state metric difference values at time “T” representing the difference between state metric values at time each preceding time “T-l” through “T-n”; and
accumulating the n state metric difference values to generate said bit-wise reliability values.
8. The method of claim 6
wherein the nT Viterbi decoder is a 2T Viterbi decoder, and
wherein the step of generating said bit-wise reliability value further comprises:
generating state metric difference values at time “T” representing the difference between state metric values at time “T-l” and at time “T- 2 ”; and
accumulating the state metric difference values to generate said bit-wise reliability values.
9. A digital channel decoder circuit comprising:
an nT soft output Viterbi element adapted to receive an input signal on each pulse of a corresponding clock signal, the received input signal representing a sequence of n bits of an encoded symbol, the Viterbi element adapted to generate a most likely decoded symbol and adapted to generate a bit-wise reliability value for each bit of the decoded symbol,
wherein the nT soft output Viterbi algorithm element further comprises:
nT branch metric information; and
a 1T state metric difference computation element for generating and accumulating 1T state metric difference information derived from the nT branch metric information.
10. The decoder of claim 9 wherein the nT soft output Viterbi algorithm element is a 2T soft output Viterbi algorithm element and further comprises:
2T branch metric information; and
a 1T state metric difference computation element for generating and accumulating 1T state metric difference information derived from the 2T branch metric information.