Power saving flip-flop

1. A scannable flip-flop comprising:

a clock input;

a normal data input and a test data input;

a normal data output and a scan data output;

a normal operating mode during which the normal data output is enabled and the scan data output outputs a first logic value that remains constant when the clock input changes;

a scan-shift mode during which the normal data output outputs a second logic value that remains constant when the clock input changes and the scan data output is enabled, and

wherein the first and second logic values are selected to be one of equivalent or not equivalent.

2. The scannable flip-flop of claim 1 and further comprising:

a test enable input;

a logic block, which receives the normal data input and the test data input and has a logic block output;

a latch, which latches the logic block output in response to the clock input and has a latch output; and

a gating circuit, which gates the latch output to the normal data output and to the scan data output separately as a function of the test enable input.

3. The scannable flip-flop of claim 2 wherein the logic block comprises:

a multiplexer, which selectively applies the normal data input or the test data input to the latch as a function of the test enable input.

4. The scannable flip-flop of claim 2 wherein the latch comprises a D-type flip-flop.

5. The scannable flip-flop of claim 2 wherein the gating circuit comprises:

a first circuit, which passes the latch output to the normal data output when the test enable input has an inactive state and blocks the latch output from reaching the normal data output when the test enable input has an active state; and

a second circuit, which passes the latch output to the scan data output when the test enable input has the active state and blocks the latch output from reaching the scan data output when the test enable input has the inactive state.

6. The scannable flip-flop of claim 2 wherein the first and second logic values are selected to be equivalent and wherein the gating circuit comprises:

a first logic-AND gate, which gates the latch output with a complement of the test enable input and has an output coupled to the normal data output; and

a second logic-AND gate, which gates the latch output with the test enable input and has an output coupled to the scan data output.

7. The scannable flip-flop of claim 2 wherein the first and second logic values are selected to be equivalent and wherein the gating circuit comprises:

a logic-OR gate, which gates the latch output with the test enable input and has an output coupled to the normal data output; and

a logic-AND gate, which gates the latch output with the test enable input and has an output coupled to the scan data output.

8. A scannable flip-flop comprising:

a clock input;

a normal data input and a test data input;

a normal data output and a scan data output;

a normal operating mode during which the normal data output is enabled and the scan data output disabled;

a scan-shift mode during which the normal data output is disabled and the scan data output is enabled;

a test enable input;

a logic block, which receives the normal data input and the test data input and has a logic block output;

a latch, which latches the logic block output in response to the clock input and has a latch output; and

a gating circuit, which gates the latch output to the normal data output and to the scan data output separately as a function of the test enable input and wherein the logic block comprises:

an exclusive-NOR gate having a first input coupled to the normal data input, a second input coupled to the test data input and an output coupled to the latch.

9. A scannable flip-flop comprising:

a clock input;

a normal data input and a test data input;

a normal data output and a scan data output;

a normal operating mode during which the normal data output is enabled and the scan data output disabled;

a scan-shift mode during which the normal data output is disabled and the scan data output is enabled;

a test enable input;

a logic block, which receives the normal data input and the test data input and has a logic block output;

a latch, which latches the logic block output in response to the clock input and has a latch output; and

a gating circuit, which gates the latch output to the normal data output and to the scan data output separately as a function of the test enable input and wherein the gating circuit comprises:

a first logic-OR gate, which gates the latch output with the test enable input and has an output coupled to the normal data output; and

a second logic-OR gate, which gates the latch output with a complement of the test enable input and has an output coupled to the scan data output.

10. A scannable flip-flop comprising:

a normal data input and a test data input;

a normal data output and a scan data output; and

a test enable input, which has an inactive state in which the normal data input is selectively coupled to the normal data output and the scan data output outputs a first logic value that remains constant, and which has an active state in which the test data input is selectively coupled to the scan data output and the normal data output outputs a second logic value that remains constant, and

wherein the first and second logic values are selected to be one of equivalent or not equivalent.

11. The scannable flip-flop of claim 10 and further comprising:

a logic block, which receives the normal data input and the test data input and has a logic block output;

a latch, which latches the logic block output and has a latch output; and

a gating circuit, which gates the latch output to the normal data output and to the scan data output separately as a function of the test enable input.

12. The scannable flip-flop of claim 11 wherein the logic block comprises:

a multiplexer, which selectively applies the normal data input or the test data input to the latch as a function of the test enable input.

13. The scannable flip-flop of claim 11 and further comprising a clock input and wherein the latch comprises a D-type flip-flop, which latches data to the latch output in response to the clock input.

14. The scannable flip-flop of claim 11 wherein the gating circuit comprises:

a first circuit, which passes the latch output to the normal data output when the test enable input has the inactive state and blocks the latch output from reaching the normal data output when the test enable input has the active state; and

a second circuit, which passes the latch output to the scan data output when the test enable input has the active state and blocks the latch output from reaching the scan data output when the test enable input has the inactive state.

15. A scannable flip-flop comprising:

a normal data input and a test data input;

a normal data output and a scan data output;

a test enable input, which has an inactive state in which the normal data input is selectively coupled to the normal data output and the scan data output is disabled to a first logic value, and which has an active state in which the test data input is selectively coupled to the scan data output and the normal data output is disabled;

a logic block, which receives the normal data input and the test data input and has a logic block output;

a latch, which latches the logic block output and has a latch output; and

a gating circuit, which gates the latch output to the normal data output and to the scan data output separately as a function of the test enable input and wherein the logic block comprises:

an exclusive-NOR gate having a first input coupled to the normal data input, a second input coupled to the test data input and an output coupled to the latch.

16. A scannable flip-flop comprising:

a normal data input and a test data input;

a normal data output and a scan data output;

a test enable input, which has an inactive state in which the normal data input is selectively coupled to the normal data output and the scan data output is disabled to a first logic value, and which has an active state in which the test data input is selectively coupled to the scan data output and the normal data output is disabled;

a logic block, which receives the normal data input and the test data input and has a logic block output;

a latch, which latches the logic block output and has a latch output; and

a gating circuit, which gates the latch output to the normal data output and to the scan data output separately as a function of the test enable input and wherein the gating circuit comprises:

a first logic gate, which gates the latch output with at least one of the test enable input or a complement of the test enable input, and has an output coupled to the normal data output; and

a second logic gate, which gates the latch output with at least one of the test enable input or a complement of the test enable input, and has an output coupled to the scan data output.

17. A method comprising:

applying a normal data input, a test data input, and a test enable input to a flip-flop;

latching the normal data input to a normal data output of the flip-flop in response to a clock signal and outputting a constant first logic value at a scan data output of the flip-flop when the test enable input has an inactive state; and

latching the test data input to the scan data output in response to the clock signal and outputting a constant second logic value at the normal data output when the test enable input has an active state and wherein the first and second logic values are selected to be one of equivalent or not equivalent.

18. The method of claim 17 and further comprising:

multiplexing the normal data input with the test data input as a function of the test enable input.

19. A method comprising:

applying a normal data input, a test data input, and a test enable input to a flip-flop;

latching the normal data input to a normal data output of the flip-flop in response to a clock signal and disabling a scan data output of the flip-flop when the test enable input has an inactive state; and

latching the test data input to the scan data output in response to the clock signal and disabling the normal data output when the test enable input has an active state; and

applying the normal data input and the test data input to the inputs of a logic equivalence circuit, wherein the steps of latching comprise latching an output of the equivalence circuit.