System to reduce programmable range specifications for a given target accuracy in calibrated electronic circuits
An apparatus comprising a comparator circuit, a reference circuit, a plurality of elements and a logic circuit. The comparator circuit may be configured to generate a difference signal in response to (i) a reference signal and (ii) a test signal. The reference circuit configured to generate the reference signal in response to a first control signal. The plurality of elements may each be configured to generate an intermediate test signal. One of the intermediate test signals may be presented as the test signal by activating one of the test elements, in response to a second control signal. The logic circuit may be configured to generate (i) the first control signal and (ii) the second control signal, each in response to the difference signal.
1. An apparatus comprising:
a comparator circuit configured to generate a difference signal in response to (i) a reference signal and (ii) a test signal;
a reference circuit configured to generate said reference signal in response to a first control signal;
a plurality of elements each configured to generate an intermediate test signal, wherein one of said intermediate test signals is presented as said test signal by activating one of said elements, in response to a second control signal; and
a logic circuit configured to generate (i) said first control signal and (ii) said second control signal, each in response to said difference signal, wherein (A) said plurality of elements are sequentially tested until each of said plurality of elements have been tested, (B) said comparator circuit generates an individual difference signal for each of said plurality of elements, (C) said logic circuit generates an output signal in response to each of said individual difference signals, (D) said output signal comprises an average of said individual difference signals, and (E) said output signal comprises an error signal.
2. The apparatus according to claim 1 , wherein said second control signal comprises a multi-bit control signal, wherein each bit of said multi-bit control signal is configured to enable one of said elements.
3. The apparatus according to claim 1 , wherein said individual difference signals each comprise a manufacturing parameter being tested by said apparatus.
4. The apparatus according to claim 1 , wherein said reference signal is adjusted in response to said output signal.
5. The apparatus according to claim 1 , wherein said elements each comprise current elements used to implement a portion of an integrated circuit.
6. The apparatus according to claim 1 , wherein each of said plurality of elements has (i) a fixed portion and (ii) a programmable portion, wherein said programmable portion is adjustable in response to said second control signal.
7. An apparatus comprising:
means for generating a difference signal in response to (i) a reference signal and (ii) a test signal;
means for generating said reference signal in response to a first control signal;
a plurality of elements each configured to generate an intermediate test signal, wherein one of said intermediate test signals is presented as said test signal by activating one of said elements, in response to a second control signal; and
means for generating (i) said first control signal and (ii) said second control signal, each in response to said difference signal, wherein (i) said plurality of elements are sequentially tested until each of said plurality of elements have been tested, (ii) means for generating said difference signal generates an individual difference signal for each of said plurality of elements, (iii) means for generating said first and second control signals generates an output signal in response to each of said individual difference signals, (iv) said output signal comprises an average of said individual difference signals, and (v) said output signal comprises an error signal.
8. A method for calibrating elements in an integrated circuit comprising the steps of:
(A) generating a difference signal in response to (i) a reference signal and (ii) a test signal;
(B) generating said reference signal in response to a first control signal using a reference circuit;
(C) generating an intermediate test signal using a plurality of elements, wherein one of said intermediate test signals is presented as said test signal by activating one of said elements, in response to a second control signal; and
(D) generating (i) said first control signal and (ii) said second control signal, each in response to said difference signal, wherein (i) said plurality of elements are sequentially tested until each of said plurality of elements have been tested, (ii) step (A) generates an individual difference signal for each of said plurality of elements, (iii) step (C) generates an output signal in response to each of said individual difference signals, (iv) said output signal comprises an average of said individual difference signals, and (v) said output signal comprises an error signal.
9. The method according to claim 8 , wherein said second control signal comprises a multi-bit control signal, wherein each bit of said multi-bit control signal is configured to enable one of said elements.
10. The method according to claim 8 , wherein said plurality of elements are sequentially tested until each of said plurality of elements have been tested.
11. The method according to claim 10 , wherein step (A) generates an individual difference signal for reach of said plurality of elements.
12. The method according to claim 11 , wherein step (D) generates an output signal in response to each of said individual difference signals.
13. The method according to claim 12 , wherein said output signal comprises an average of said individual difference signals.
14. The method according to claim 13 , wherein said individual difference signals each comprise a manufacturing parameter being tested by said apparatus.
15. The method according to claim 14 , wherein said reference signal is adjusted in response to said output signal.