Circuit and method for loop control

1 . A loop control circuit to control to repeatedly execute from a loop start instruction to a loop end instruction according to a loop instruction in a processor to process an instruction in a pipeline, the loop control circuit comprising:

an interlock generation circuit to suspend a pipeline process of the loop end instruction until a pipeline process of the loop instruction is completed;

a loop end evaluation circuit to take a loop end evaluation when the pipeline process of the loop end instruction is executed.

2 . The loop control circuit according to claim 1 , further comprising:

a program counter to sequentially indicate an address of an instruction to be processed in pipeline;

a loop start address calculation circuit to calculate a loop start address during the pipeline process of the loop instruction, the loop start address being an address of the loop start instruction;

a loop end address calculation circuit to calculate a loop end address during the pipeline process of the loop instruction, the loop end address being an address of the loop end instruction; and,

the loop end evaluation circuit sets the program counter to the loop start address according to a result of the comparison between the program counter and the loop end address after the pipeline process of the loop instruction is completed.

3 . The loop control circuit according to claim 1 , wherein the interlock generation circuit generates an interlock from a phase following a decode phase to a completion of an execution phase in the pipeline process of the loop instruction so as to suspend a pipeline process of the loop start instruction.

4 . The loop control circuit according to claim 2 , wherein the interlock generation circuit generates an interlock from a phase following a decode phase to a completion of an execution phase in the pipeline process of the loop instruction so as to suspend a pipeline process of the loop start instruction.

5 . The loop control circuit according to claim 3 , wherein the loop start address calculation circuit calculates the loop start address in a pipeline phase among pipeline phases included in the pipeline process of the loop instruction, the pipeline phase being the phase the address of the loop start instruction is set to the program counter.

6 . The loop control circuit according to claim 4 , wherein the loop start address calculation circuit calculates the loop start address in a pipeline phase among pipeline phases included in the pipeline process of the loop instruction, the pipeline phase being the phase the address of the loop start instruction is set to the program counter.

7 . The loop control circuit according to claim 3 , further comprising a loop start address register and a temporary loop start address register to hold the loop start address,

wherein the loop start address calculation circuit stores the calculated loop start address to the temporary loop start address register, and

the loop start address calculation circuit stores the loop start address stored to the temporary loop start address to the loop start address register at a completion of the pipeline process of the loop instruction.

8 . The loop control circuit according to claim 1 , wherein the interlock generation circuit generates an interlock from the phase following the decode phase to the completion of an execution phase in the pipeline process of the loop instruction so as to suspend a pipeline process of the loop end instruction.

9 . The loop control circuit according to claim 2 , wherein the interlock generation circuit generates an interlock from the phase following the decode phase to the completion of an execution phase in the pipeline process of the loop instruction so as to suspend a pipeline process of the loop end instruction.

10 . The loop control circuit according to claim 8 , wherein the interlock generation circuit generates an interlock if the pipeline process of the loop end instruction is executed before the completion of the pipeline process of the loop instruction.

11 . The loop control circuit according to claim 9 , wherein the interlock generation circuit generates an interlock if the pipeline process of the loop end instruction is executed before the completion of the pipeline process of the loop instruction.

12 . The loop control circuit according to claim 8 , further comprising a loop start address register and a temporary loop start address register to hold the loop start address, and a loop end address register and a temporary loop end address register to hold the loop end address,

wherein the loop start address calculation circuit stores the loop start address in a pipeline phase among the pipeline phases included in the pipeline process of the loop instruction to the temporary loop start address register, the loop start register being calculated

the loop start address calculation circuit stores the loop start address calculated in a pipeline phase among pipeline phases included in the pipeline process of the loop instruction, the pipeline phase being the phase the address of the loop start instruction is set to the program counter,

the loop end address calculation circuit stores the loop end address calculated in any of a pipeline phase from the phase following the decode phase to the execution phase among the pipeline phases included in the pipeline process of the loop instruction to the temporary loop end address register, and

wherein the loop start address calculation circuit stores the loop start address stored to the temporary loop start address to the loop start address register and the loop end address calculation circuit stores the loop end address stored to the temporary loop end address to the loop end address register at a completion of the pipeline process of the loop instruction.

13 . The loop control circuit according to claim 10 , further comprising a loop start address register and a temporary loop start address register to hold the loop start address, and a loop end address register and a temporary loop end address register to hold the loop end address,

wherein the loop start address calculation circuit stores the loop start address in a pipeline phase among the pipeline phases included in the pipeline process of the loop instruction to the temporary loop start address register, the loop start register being calculated

the loop start address calculation circuit stores the loop start address calculated in a pipeline phase among pipeline phases included in the pipeline process of the loop instruction, the pipeline phase being the phase the address of the loop start instruction is set to the program counter,

the loop end address calculation circuit stores the loop end address calculated in any of a pipeline phase from the phase following the decode phase to the execution phase among the pipeline phases included in the pipeline process of the loop instruction to the temporary loop end address register, and

wherein the loop start address calculation circuit stores the loop start address stored to the temporary loop start address to the loop start address register and the loop end address calculation circuit stores the loop end address stored to the temporary loop end address to the loop end address register at a completion of the pipeline process of the loop instruction.

14 . A loop control circuit to control to repeatedly execute from a loop start instruction to a loop end instruction according to a loop instruction in a processor to process an instruction in a pipeline, the loop control circuit comprising:

a program counter to sequentially indicate an address of an instruction to be processed in pipeline;

a loop end address calculation circuit to calculate a loop end address, the loop end address being an address of the loop end instruction; and

an interlock generation circuit to generate an interlock according to a result of a comparison between the program counter and the loop end address until a completion of the pipeline process of the loop instruction so as to suspend the pipeline process of the loop end instruction.

15 . The loop control circuit according to claim 14 , comprising:

a loop start address calculation circuit to calculate the loop start address in a pipeline phase among pipeline phases included in the pipeline process of the loop instruction, the pipeline phase being the phase the address of the loop start instruction is set to the program counter; and

a loop end evaluation circuit to set the program counter to the loop start address according to a result of the comparison between the program counter and the loop end address after completing the pipeline process of the loop instruction.

16 . The loop control circuit according to claim 14 , wherein the interlock generation circuit generates an interlock if the calculated loop end address is equal to the program counter.

17 . The loop control circuit according to claim 15 , wherein the interlock generation circuit generates an interlock if the calculated loop end address is equal to the program counter.

18 . A loop control method to control to repeatedly execute from a loop start instruction to a loop end instruction according to a loop instruction in a processor to process an instruction in a pipeline, the loop control method comprising:

generating an interlock to suspend a pipeline process of the loop end instruction until a pipeline process of the loop instruction is completed.

19 . A loop control method according to claim 18 , further comprising:

indicating sequentially an address of an instruction to be processed in pipeline by a program counter;

calculating a loop end address, the loop end address being an address of the loop end instruction,

the processing of generating an interlock is according to a result of the comparison between the program counter and the calculated loop end address.

20 . The loop control method according to claim 19 , further comprising generating an interlock if the calculated loop end address is equal to an address indicated by the program counter until a completion of the pipeline process of the loop instruction.