Cascode-type current mode comparator and receiver, and semiconductor device having the same
A current mode comparator for a semiconductor device is disclosed. The current mode comparator may include a logic circuit coupled to a voltage sensing node, a first cascode coupled to the voltage sensing node and a first power node, and a second cascode coupled to the voltage sensing node and a second power node. The logic circuit may convert a voltage of the voltage sensing node to an output signal.
1. A current mode comparator comprising:
a logic circuit coupled to a voltage sensing node, the logic circuit converting a voltage of the voltage sensing node to an output signal;
a first cascode coupled to the voltage sensing node and a first power node; and
a second cascode coupled to the voltage sensing node and a second power node,
wherein the first cascode and the second cascode are turned on and/or off based on the output signal.
2. The current mode comparator of claim 1 , wherein the output signal is a CMOS level output signal.
3. The current mode comparator of claim 1 , wherein the output signal reflects a difference between a reference current and a data current.
4. The current mode comparator of claim 1 , wherein the logic circuit is a CMOS logic circuit.
5. The current mode comparator of claim 4 , wherein the CMOS logic circuit includes at least two NAND gates, the output of one of the at least two NAND gates providing the output signal.
6. The current mode comparator of claim 1 , wherein:
the first cascode supplies a first current from the first power node to the voltage sensing node; and
the second cascode supplies a second current from the voltage sensing node to the second power node.
7. The current mode comparator of claim 6 , wherein:
the first current is equivalent to the difference between a data current and a reference current; and
the second current is equivalent to the difference between the reference current and the data current.
8. The current mode comparator of claim 1 , wherein:
the first cascode includes a first cascode current source and a first main transistor; and
the second cascode includes a second cascode current source and a second main transistor.
9. The current mode comparator of claim 8 , wherein:
the first cascode current source includes a PMOS transistor having a first terminal coupled to the first main transistor and a second terminal coupled to the voltage sensing node; and
the second cascode current source includes an NMOS transistor having a first terminal coupled to the second main transistor and a second terminal coupled to the voltage sensing node.
10. The current mode comparator of claim 8 , wherein:
the first cascode current source includes a PMOS transistor having a first terminal coupled to the first main transistor and a second terminal receiving a first bias voltage; and
the second cascode current source includes an NMOS transistor having a first terminal coupled to the second main transistor and a second terminal receiving a second bias voltage.
11. A current mode receiver comprising:
the current mode comparator of claim 1 ; and
a signal receiving end coupled to the voltage sensing node.
12. The current mode receiver of claim 11 wherein the signal receiving end receives a reference current and a data current, and generates a sensing voltage based on a difference between the reference current and the data current.
13. The current mode receiver of claim 11 wherein the signal receiving end receives a reference voltage and a data current, generates a reference current from the reference voltage, and generates a sensing voltage based on a difference between the reference current and the data current.
14. The current mode receiver of claim 11 , further comprising:
a reference voltage generating circuit generating a reference voltage; and
a cascode bias circuit generating a first bias voltage and a second bias voltage.
15. The current mode receiver of claim 14 , wherein:
the first cascode includes a PMOS transistor having a first terminal coupled to a first main transistor and a second terminal receiving the first bias voltage; and
the second cascode includes an NMOS transistor having a first terminal coupled to a second main transistor and a second terminal receiving the second bias voltage.
16. The current mode receiver of claim 14 , wherein:
the cascode bias circuit generates a first bias current corresponding to 1/n of the reference current in response to the reference voltage, where n is a real number greater than 1;
the cascode bias circuit generates the first bias voltage such that a current from the first cascode corresponds to m/n of the first bias current;
the cascode bias circuit generates the second bias voltage such that a current from the second cascode corresponds to m/n of the first bias current;
m is the W/L ratio of a cascode transistor of the first cascode; and
n is a real number greater than 1.
17. A semiconductor device comprising a plurality of the current mode receivers of claim 11 .
18. The semiconductor device of claim 17 , wherein the signal receiving end receives a reference current and a data current, and generates a sensing voltage based on a difference between the reference current and the data current.
19. The semiconductor device of claim 17 , wherein the signal receiving end receives a reference voltage and a data current, generates a reference current from the reference voltage, and generates a sensing voltage based on a difference between the reference current and the data current.
20. The semiconductor device of claim 17 , further comprising:
at least one reference voltage generating circuit generating a reference voltage, the signal receiving end receiving the reference voltage.