LDPC (Low Density Parity Check) coded modulation hybrid decoding
View Patent ↗LDPC (Low Density Parity Check) coded modulation hybrid decoding. A novel approach is presented wherein a combination of bit decoding and symbol level decoding (e.g., hybrid decoding) is performed for LDPC coded signals. Check node updating and symbol node updating are successively and alternatively performed on bit edge messages for a predetermined number of decoding iterations or until a sufficient degree of precision is achieved. The symbol node updating of the bit edge messages involves using symbol metrics corresponding to the symbol being decoded as well as the bit edge messages most recently updated by check node updating. The check node updating of the bit edge messages involves using the bit edge messages most recently updated by symbol node updating. The symbol node updating also involves computing possible soft symbol estimates for the symbol during each decoding iteration.
1. A decoder that is operable to perform hybrid decoding of an LDPC (Low Density Parity Check) coded signal, the decoder comprising:
a symbol sequence estimate and symbol update module that is operable to update a bit edge message using a symbol metric corresponding to a symbol of the LDPC coded signal and a first check edge message; and
a check node update module that is operable to update the first check edge message using the updated bit edge message thereby generating a second check edge message; and wherein:
the symbol sequence estimate and symbol update module is operable to make a soft estimate of the symbol of the LDPC coded signal using the symbol metric and the second check edge message.
2. The decoder of claim 1 , further comprising:
a symbol metric computer that is operable to calculate the symbol metric corresponding to the symbol of the LDPC coded signal.
3. The decoder of claim 1 , further comprising:
a bit edge message initialization module that is operable to calculate an initial LLR (log likelihood ratio) bit edge message corresponding to a bit of the LDPC coded signal for use by the symbol sequence estimate and symbol update module when performing a first decoding iteration.
4. The decoder of claim 1 , further comprising:
a hard limiter that is operable to process the soft estimate of the symbol of the LDPC coded signal thereby making a best estimate of an individual bit within the symbol of the LDPC coded signal.
5. The decoder of claim 1 , further comprising:
a syndrome calculator that is operable to determine whether all syndromes of an LDPC code by which the LDPC coded signal is generated have passed during each decoding iteration of a plurality of decoding iterations; and wherein:
if at least one syndrome of the LDPC code fails as determined by the syndrome calculator, the decoder is operable to perform at least one additional decoding iteration.
6. The decoder of claim 1 , further comprising:
a syndrome calculator that is operable to determine whether all syndromes of an LDPC code by which the LDPC coded signal is generated have passed; and wherein:
the symbol sequence estimate and symbol update module and the check node update module operate cooperatively by alternatively and successively performing a plurality of decoding iterations to update bit edge messages and check edge messages, respectively;
if at least one syndrome of the LDPC code fails as determined by the syndrome calculator, the symbol sequence estimate and symbol update module and the check node update module operate to perform at least one additional decoding iteration of the plurality of decoding iterations; and
if all syndromes of the LDPC code pass as determined by the syndrome calculator, the symbol sequence estimate and symbol update module and the check node update module operate have performed a final decoding iteration of the plurality of decoding iterations.
7. The decoder of claim 1 , wherein:
the symbol sequence estimate and symbol update module and the check node update module operate cooperatively by alternatively and successively performing a predetermined plurality of decoding iterations to update bit edge messages and check edge messages, respectively.
8. The decoder of claim 1 , wherein:
the LDPC coded signal is a variable modulation signal;
a first symbol of LDPC coded signal is mapped according to a first modulation that includes a first constellation and a corresponding first mapping; and
a second symbol of the LDPC coded signal is mapped according to a second modulation that includes a second constellation and a corresponding second mapping.
9. The decoder of claim 1 , wherein:
the LDPC coded signal is a variable code rate signal;
a first symbol of the LDPC coded signal is encoded according to a first code rate; and
a second symbol of the LDPC coded signal is encoded according to a second code rate.
10. The decoder of claim 1 , wherein:
the decoder is implemented within a communication device; and
the communication device is implemented within at least one of a satellite communication system, an HDTV (High Definition Television) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, a fiber-optic communication system, a WLAN (Wireless Local Area Network) communication system, and a DSL (Digital Subscriber Line) communication system.
11. A decoder that is operable to perform hybrid decoding of an LDPC (Low Density Parity Check) coded signal, the decoder comprising:
a symbol metric computer that is operable to calculate a symbol metric corresponding to a symbol of the LDPC coded signal;
a symbol sequence estimate and symbol update module that is operable to update a bit edge message using the symbol metric and a first check edge message of a previous decoding iteration; and
a check node update module that is operable to:
update the first check edge message using the updated bit edge message thereby generating a second check edge message; and
make a soft estimate of the symbol of the LDPC coded signal using the symbol metric and the second check edge message; and
a hard limiter that is operable to process the soft estimate of the symbol of the LDPC coded signal thereby making a best estimate of an individual bit within the symbol of the LDPC coded signal.
12. The decoder of claim 11 , further comprising:
a bit edge message initialization module that is operable to calculate an initial LLR (log likelihood ratio) bit edge message corresponding to a bit of the LDPC coded signal for use by the symbol sequence estimate and symbol update module when performing a first decoding iteration.
13. The decoder of claim 11 , further comprising:
a syndrome calculator that is operable to determine whether all syndromes of an LDPC code by which the LDPC coded signal is generated have passed during each decoding iteration of a plurality of decoding iterations; and wherein:
if at least one syndrome of the LDPC code fails as determined by the syndrome calculator, the decoder is operable to perform at least one additional decoding iteration.
14. The decoder of claim 11 , wherein:
the symbol sequence estimate and symbol update module and the check node update module operate cooperatively by alternatively and successively performing a predetermined plurality of decoding iterations to update bit edge messages and check edge messages, respectively.
15. The decoder of claim 11 , wherein:
the LDPC coded signal is a variable modulation signal;
a first symbol of LDPC coded signal is mapped according to a first modulation that includes a first constellation and a corresponding first mapping; and
a second symbol of the LDPC coded signal is mapped according to a second modulation that includes a second constellation and a corresponding second mapping.
16. The decoder of claim 11 , wherein:
the LDPC coded signal is a variable code rate signal;
a first symbol of the LDPC coded signal is encoded according to a first code rate; and
a second symbol of the LDPC coded signal is encoded according to a second code rate.
17. The decoder of claim 11 , wherein:
the decoder is implemented within a communication device; and
the communication device is implemented within at least one of a satellite communication system, an HDTV (High Definition Television) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, a fiber-optic communication system, a WLAN (Wireless Local Area Network) communication system, and a DSL (Digital Subscriber Line) communication system.
18. A method for performing hybrid decoding of an LDPC (Low Density Parity Check) coded signal, the method comprising:
calculating a symbol metric corresponding to a symbol of the LDPC coded signal;
updating a bit edge message using the symbol metric and a first check edge message;
updating the first check edge message using the updated bit edge message thereby generating a second check edge message; and
making a soft estimate of the symbol of the LDPC coded signal using the symbol metric and the second check edge message.
19. The method of claim 18 , further comprising:
hard limiting the soft estimate of the symbol of the LDPC coded signal thereby making a best estimate of an individual bit within the symbol of the LDPC coded signal.
20. The method of claim 18 , further comprising:
determining whether all syndromes of an LDPC code by which the LDPC coded signal is generated have passed during each decoding iteration of a plurality of decoding iterations; and
if at least one syndrome of the LDPC code fails, performing at least one additional decoding iteration.