IP Library Granted Patent US 7,609,562
Granted Patent B2
US 7,609,562 · App. 11/701,302 · Granted Oct 27, 2009

Configurable device ID in non-volatile memory

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Quick Facts
Patent No.
US 7,609,562
App. No.
11/701,302
Granted
Oct 27, 2009
Kind
B2
Abstract

Various embodiments of the invention may use one or more programmable non-volatile registers in each memory device to provide a separate device address for that device. These registers may be programmed at various points in the manufacturing and distribution cycle, such as but not limited to the memory chip factory, an original equipment manufacturer (OEM), or in the field. In some embodiments, other types of information (e.g., configuration information for the memory device) may also be programmed in this manner.

Claims (21)

1. A method, comprising:

issuing one or more signals to select a particular non-volatile memory device;

directing the selected memory device to program an address register within the selected memory device;

issuing an address to the selected memory device for the selected memory device to store in the address register; and

verifying the address was correctly stored in the selected memory device;

wherein the address stored in the memory device is to serve as a selection address for the memory device.

2. The method of claim 1 , wherein said issuing one or more signals comprises issuing a selection command.

3. The method of claim 1 , wherein said issuing one or more signals comprises asserting a programming signal.

4. The method of claim 1 , wherein said directing comprises issuing a command to the non-volatile memory device.

5. The method of claim 4 , wherein said command and said address are issued on a same set of input/output lines.

6. An article comprising

a tangible machine-readable medium that contains instructions, which when executed by one or more processors result in performing operations comprising:

issuing one or more signals to select a particular non-volatile memory device;

directing the selected memory device to program an address register within the selected memory device;

issuing an address to the selected memory device for the selected memory device to store in the address register; and

verifying the address was correctly stored in the selected memory device;

wherein the address stored in the memory device is to serve as a selection address for the memory device;

wherein the operation of issuing one or more signals comprises asserting a programming signal.

7. The article of claim 6 , wherein the operation of issuing one or more signals comprises issuing a selection command.

8. The article of claim 6 , wherein the operation of directing comprises issuing a command to the non-volatile memory device.

9. The article of claim 6 , wherein said command and said address are issued on a same set of input/output lines.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2023
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP.
Reel/Frame 062437/0329 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 8, 2009
From: SUNDARAM, RAJESH
To: INTEL CORPORATION
Reel/Frame 023201/0683 →