Transistor structures and methods for making the same
View Patent ↗Enhancement mode, field effect transistors wherein at least a portion of the transistor structure may be substantially transparent. One variant of the transistor includes a channel layer comprising a substantially insulating, substantially transparent, material selected from ZnO or SnO 2 . A gate insulator layer comprising a substantially transparent material is located adjacent to the channel layer so as to define a channel layer/gate insulator layer interface. A second variant of the transistor includes a channel layer comprising a substantially transparent material selected from substantially insulating ZnO or SnO 2 , the substantially insulating ZnO or SnO 2 being produced by annealing. Devices that include the transistors and methods for making the transistors are also disclosed.
1. A method for making an enhancement mode, field effect transistor comprising:
depositing ZnO or SnO 2 onto at least a portion of a surface of a gate insulating layer; and
annealing the deposited ZnO or SnO 2 for about 1 to about 5 minutes at a temperature of about 300 to about 1000° C. in an oxidative or inert atmosphere to make a layer comprising ZnO or SnO 2 .
wherein the field effect transistor exhibits an optical transmission through the field effect transistor of at least about 70% in the visible portion of the electromagnetic spectrum.
2. The method according to claim 1 , wherein ZnO is deposited.
3. The method according to claim 1 , wherein SnO 2 is deposited and the method further comprises introducing an acceptor dopant into the SnO 2 .
4. The method according to claim 1 , wherein the gate insulator layer comprises a substantially transparent material.
5. The method according to claim 1 , wherein the annealing temperature is about 700 to about 800° C.
6. The method according to claim 1 , further comprising depositing on the ZnO or SnO 2 layer at least one material for forming a source and a drain.
7. The method according to claim 1 , further comprising depositing on the gate insulating layer at least one material for forming a source and a drain prior to depositing the ZnO or SnO 2 .
8. The method according to claim 1 , wherein the ZnO is not doped.
9. The method according to claim 1 , wherein the ZnO or SnO 2 is annealed in an oxidative atmosphere.
10. The method according to claim 1 , wherein the ZnO or SnO 2 is annealed in an inert atmosphere.
11. The method according to claim 1 , wherein the deposited and annealed ZnO or SnO 2 forms a substantially insulating, substantially transparent, material.
12. The method according to claim 1 , wherein the layer comprising ZnO or SnO 2 is a channel layer.
13. The method according to claim 2 , wherein the ZnO is vapor deposited.
14. The method according to claim 3 , wherein the SnO 2 is vapor deposited.
15. The method according to claim 6 , further comprising annealing the source and drain material.
16. The method according to claim 7 , wherein the material for forming a source and a drain is ion beam sputtered deposited onto the gate insulating layer, and the annealing of the ZnO diffusion dopes the ZnO with the source and drain material.
17. A method for making an enhancement mode, field effect transistor comprising:
depositing ZnO or SnO 2 onto at least a portion of a surface of a gate insulating layer; and
treating the ZnO or SnO 2 such that the treated ZnO or SnO 2 has a higher resistivity and a lower oxygen vacancy concentration relative to the untreated ZnO or SnO 2 .
18. The method according to claim 17 , wherein ZnO is vapor deposited.
19. The method according to claim 13 , wherein the ZnO is chemical vapor deposited or sputtered.
20. The method according to claim 18 , wherein the ZnO is chemical vapor deposited or sputtered.
21. A method for making an enhancement mode, field effect transistor comprising:
depositing ZnO onto at least a portion of a surface of a gate insulating layer; and
annealing the deposited ZnO for about 1 to about 5 minutes at a temperature of about 300 to about 1000° C. in an oxidative or inert atmosphere,
wherein the field effect transistor exhibits an optical transmission through the field effect transistor of at least about 70% in the visible portion of the electromagnetic spectrum.
22. The method according to claim 21 , wherein the ZnO is vapor deposited.
23. The method according to claim 21 , wherein the deposited and annealed ZnO forms a substantially insulating, substantially transparent, material.
24. A method for making an enhancement mode, field effect transistor comprising:
depositing ZnO or SnO 2 onto at least a portion of a surface of a gate insulating layer; and
annealing the ZnO or SnO 2 for about 1 to about 5 minutes at a temperature of about 300 to about 1000° C. in an oxidative atmosphere to make a layer comprising ZnO or SnO 2 .
25. A method for making an enhancement mode, field effect transistor comprising:
depositing ZnO or SnO 2 onto at least a portion of a surface of a gate insulating layer; and
annealing the deposited ZnO or SnO 2 for about 1 to about 5 minutes at a temperature of about 300 to about 1000° C. in an oxidative or inert atmosphere to make a layer comprising ZnO or SnO 2 ,
wherein the method further comprises depositing on the gate insulating layer at least one material for forming a source and a drain prior to depositing the ZnO or SnO 2 .
26. A method for making an enhancement mode, field effect transistor comprising:
depositing ZnO or SnO 2 onto at least a portion of a surface of a gate insulating layer; and
annealing the deposited ZnO or SnO 2 for about 1 to about 5 minutes at a temperature of about 300 to about 1000° C. in an oxidative or inert atmosphere to make a layer comprising ZnO or SnO 2 ,
wherein the ZnO is not doped.