Polished semiconductor wafer and process for producing it
View Patent ↗A polished semiconductor wafer has a front surface and a back surface and an edge R, which is located at a distance of a radius from a center of the semiconductor wafer, forms a periphery of the semiconductor wafer and is part of a profiled boundary of the semiconductor wafer. The maximum deviation of the flatness of the back surface from an ideal plane in a range between R-6 mm and R-1 mm of the back surface is 0.7 μm or less. A process for producing the semiconductor wafer, comprises at least one treatment of the semiconductor wafer with a liquid etchant and at least one polishing of at least a front surface of the semiconductor wafer, the etchant flowing onto a boundary of the semiconductor wafer during the treatment, and the boundary of the semiconductor wafer which faces the flow of etchant being at least partially shielded from being struck directly by the etchant. The shielding extends in the direction of a thickness d of the semiconductor wafer and is at least d+100 μm long.
1. A process for producing an etched and polished semiconductor wafer having a front surface, a back surface, and an edge, and a radius R extending from the center to the edge of the semiconductor wafer, comprising:
treating the semiconductor wafer with a liquid etchant, wherein a flow etchant is directed towards the edge of the semiconductor wafer;
at least partially shielding the edge of the semiconductor wafer from being struck directly by the flow of etchant along a distance extending in the direction of a thickness d of the semiconductor wafer, the distance having a length of at least d+100 μm and exceeding the levels of the front surface and the back surface of the semiconductor wafer; and polishing of at least a front surface of the semiconductor wafer, wherein partially shielding the edge of the semiconductor wafer comprises positioning a shield in front of the edge of the semiconductor wafer, wherein the shield does not contact the semiconductor wafer and has having a border S at a distance Δ from an inner profile end E of the edge of the semiconductor wafer.
2. The process according to claim 1 , wherein the distance Δ is at most 10 mm.
3. The process according to claim 1 , wherein the border S has a recess extending down to a depth γ to a base G of the recess, and the edge of the semiconductor wafer extending into the recess.
4. The process according to claim 1 , wherein a border of the shield which is furthest from the edge of the semiconductor wafer is rounded.
5. The process according to claim 1 , wherein the shield has a tapered body.
6. The process of claim 1 , wherein the etched and polished semiconductor wafer has a maximum deviation from flatness of the back surface from an ideal plane at a peripheral region between R-6 mm and R-1 mm of 0.7 μm or less.
7. The process of claim 6 , wherein the maximum deviation is 0.5 μm or less.
8. The process of claim 1 , wherein the wafer front surface comprises an epitaxially deposited layer.