Flash memory device with reduced drain stresses
View Patent ↗A memory device includes a matrix of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell including a transistor having a first conduction terminal, a second conduction terminal and a control terminal; a plurality of bit lines each one associated with a column, each transistor of the column having the first conduction terminal coupled with the associated bit line; a plurality of first biasing lines each one associated with a row, each transistor of the row having the control terminal coupled with the associated first biasing line; a plurality of second biasing lines each one associated with at least one row, each transistor of the at least one row having the second conduction terminal coupled with the associated second biasing line; and means for programming at least one selected memory cell belonging to a selected row. The means for programming includes first biasing means for applying a programming voltage at least to a selected first biasing line associated with the selected row, and second biasing means for applying a program enabling voltage to a selected second biasing line associated with the selected row, each memory cell being programmed only when receiving both the programming voltage and the program enabling voltage.
1. A non-volatile memory device including:
a matrix of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell including a transistor having a first conduction terminal, a second conduction terminal and a control terminal;
a plurality of bit lines each one associated with a column, each transistor of the column having the first conduction terminal coupled with the associated bit line;
a plurality of first biasing lines each one associated with a row, each transistor of the row having the control terminal coupled with the associated first biasing line;
a plurality of second biasing lines each one associated with at least one row, each transistor of the at least one row having the second conduction terminal coupled with the associated second biasing line; and
means for programming at least one selected memory cell belonging to a selected row,
wherein the means for programming includes:
first biasing means for applying a programming voltage at least to a selected first biasing line associated with the selected row, and
second biasing means for applying a program enabling voltage to a selected second biasing line associated with the selected row, each memory cell being programmed only when receiving both the programming voltage and the program enabling voltage.
2. The memory device of claim 1 , wherein the second biasing means is adapted to keep floating the unselected second biasing lines.
3. The memory device of claim 1 , wherein the first biasing means is adapted to apply the programming voltage to all the first biasing lines with the exception of a shielding subset of the first biasing lines, the first biasing lines of the shielding subset receiving substantially the same voltage as the selected second biasing line.
4. The memory device of claim 1 , wherein the first biasing means is adapted to apply the programming voltage to the selected first biasing line and to apply a compensation voltage corresponding to a threshold voltage of the programmed memory cells to the other first biasing lines with the exception of a shielding subset of the first biasing lines, the first biasing lines of the shielding subset receiving substantially the same voltage as the selected second biasing line.
5. The memory device of claim 3 , wherein the shielding subset is empty.
6. The memory device of claim 3 , wherein each second biasing line is associated with a pair of rows, the shielding subset including the first biasing line associated with the other row in the pair including the selected row.
7. The memory device of claim 3 , wherein the first biasing lines are arranged in a sequence, the shielding subset consisting of the first biasing lines adjacent in said sequence to a selected first biasing line associated with the selected row.
8. The memory device of claim 1 , wherein each transistor comprises a floating gate MOS transistor, the first conduction terminal being a drain terminal, the second conduction terminal being a source terminal, and the control terminal being a gate terminal.
9. The memory device of claim 1 , wherein the program enabling voltage is substantially equal to a reference voltage, the programming voltage is different from the reference voltage, and the compensation voltage is comprised between the program enabling voltage and the programming voltage.
10. A method for programming a non-volatile memory device including:
a matrix of memory cells arranged in a pluarlity of rows and a plurality of columns, each memory cell including a transistor having a first conduction terminal, a second conduction terminal and a control terminal;
a plurality of first biasing lines each one associated with a column, each transistor of the column having the first conduction terminal coupled with the associated bit line;
a plurality of first biasing lines each one associated with a row, each transistor of the row having the control terminal coupled with the associated first biasing line; and
plurality of second biasing lines each one associated with at least one row, each transistor of the at least one row having the second conduction terminal coupled with the associated second biasing line,
wherein the method includes:
programming at least one selected memeory cell belonging to a selected row,
wherein the programming includes:
applying a programming voltage at least to a selected first biasing line associated with the selected row; and
applying a program enabling voltage to a selected second biasing line associated with the selected row, each memory cell being programmed only when receiving both the programming voltage and the program enabling voltage.
11. A memory, comprising:
first, second, third, and forth non-volatile emeory cells each including resepective first and second conduction nodes and respective control node;
a first word line coupled to the control nodes of the first and second memeory cells;
second word line coupled to the control nodes of the third and fourth memory cells;
a first bit line coupled to the first conduction nodes of the first and third memory cells;
a second bit line coupled to the first conduction nodes of the seond and fourth memory cells;
a first bias line coupled to the second conduction nodes of the first and second memory cells;
a second bias line coupled to the second conduction nodes of the third and fourth memory cells; and
a programming circuit coupled to the word lines, bit lines, and bias lines and operable to program the first memory cell in the first row by
driving a programming voltage onto the first word line,
driving a first compensation voltage onto the seond word line,
driving a bias voltage onto the first bias line, and
causing the second bias line to have a state.
12. The memory of claim 11 wherein:
the first conduction node of each memory cell comprises a drain node; and
the second conduction node of each memory cell comprises a source node.
13. The memory of claim 11 wherein the programming circuit is operable to cause the second bias line to have the state by floating electrically the second bias line.
14. The memory of claim 11 , further comprising:
a supply node operable to receive a supply voltage;
wherein the compensation voltage substantially equals the programming voltage; and
wherein the bias voltage substantially equals the supply voltage.
15. The memory of claim 11 , further comprising:
a supply node operable to receive a supply voltage;
wherein the bias voltage substantially equals the supply voltage; and
wherein the compensation voltage is between the supply voltage and the programming voltage.
16. The memory of claim 11 wherein the compensation voltage is substantially equal to a threshold voltage of a programmed memory cell.
17. The memory of claim 11 wherein the programming circuit is further operable to program the first memory cell in the first row by:
driving a column voltage onto the first bit line; and
floating electrically the second bit line.
18. The memory of claim 11 wherein the programming circuit comprises:
a row selector coupled to the word lines;
a column selector coupled to the bit lines; and
a bias-line selector coupled to the bias lines.
19. The memory of claim 11 , further comprising:
a third word line disposes between the first and second word lines; and
wherein the programming circuit is further operable to program the first memory cell by driving the bias voltage onto the third word line.
20. The memory of claim 11 , further comprising:
a fifth memory cell including a first conduction node, a second conduction node coupled to the first bias line, and a control node;
a third word line coupled to the control node of the fifth memory cell; and
wherein the programming circuit is further operable to program the first memory cell by driving the bias voltage onto the third word line.
21. The memory of claim 11 wherein the programming circuit is:
operable to cause the second bias line to have the state by driving a second compensation voltage onto the second bias line; and
further operable to drive the second compensation voltage onto the second bit line.
22. The memory of claim 21 wherein the second compensation voltage comprises a positive voltage.
23. A system, comprising:
a controller; and
a memory coupled to the controller and comprising,
first, second, third, and fourth nonvolatile memory cells each including respective first and second conduction nodes and a respective control node;
a first word line coupled to the control nodes of the first and second memory cells;
a second word line coupled to the control nodes of the third and fourth memory cells;
a first bit line coupled to the first conduction nodes fo the first and third memory cells;
a second bit line coupled to the first conduction nodes of the second and fourth memory cells;
a first bias line coupled to the second conduction nodes of the first and second memory cells;
a second bias line coupled to the second conduction nodes of the third and fourth memory cells; and
a programming circuit coupled to the word lines, bit lines, and bias lines and operable to program the first memory cell in the first row by
driving a programming voltage onto the first word line,
driving a compensation voltage onto the second word line,
driving a bias voltage onto the first bias line, and
causing the second bias line to have a state.
24. A method for programming a first nonvolatile memory cell, comprising:
driving a programming voltage and a bias voltage onto a control node and a source node of the first memory cell; and
driving a first compensation voltage onto a control node of a second memory cell and causing a source node of the second memory cell to have a state while driving the programming and biasing voltages onto the control and source nodes of the first memory cell.
25. The method of claim 24 wherein causing the source node of the second memory cell to have a state comprises floating electrically the source node of the second memory cell.
26. The method of claim 24 , further comprising:
driving a column voltage onto a drain node of the first memeory cell; and
floating electrically a drain node of the second memory cell.
27. The method of claim 24 , further comprising driving the bias voltage onto a control node of a third memory cell disposed between the first and the second memory cell.
28. The method of claim 24 , further comprising driving the bias voltage onto a control node and a source node of a third memory cell disposed between the first and the second memory cell.
29. The method of claim 24 , further comprising:
wherein causing the source node of the second memory cell to have a state comprises driving the source node of the second memory cell to a second compensation voltage; and
driving a drain node of the second memory cell to the second compensation voltage.
30. The method of claim 24 wherein the second compensation voltage comprises a positive voltage.