Memory array programming circuit and a method for using the circuit

1. A method of programming a multi-level cell (MLC) memory array comprising deriving a programming vector associated with at least one specific program state, wherein the programming vector is derived by mapping a first pair of bits from a binary input register to a first element in the programming vector.

2. The method according to claim 1 , wherein each element in the programming vector corresponds to a single charge storage region of an MLC in the memory array.

3. The method according to the claim 2 , further comprising mapping a second pair of bits from a binary input register to a second element in a programming vector.

4. The method according to claim 1 , wherein mapping a pair of bits to an element of the programming vector comprises setting the element value to a “program” value if the pair of bits corresponds to the at least one specific program state with which the programming vector is associated.

5. The method according to claim 1 , wherein mapping a pair of bits to an element of said programming vector comprises setting the element value to a “do-not-program” value if said pair of bits does not correspond to the at least one specific program state with which the programming vector is associated.

6. The method according to claim 1 , wherein the vector is associated with each of two or more specific program states.

7. The method according to claim 6 , wherein the two or more specific program states comprise at least a first program state and a second program state, wherein the second program state is associated with a higher threshold voltage than the first program state.

8. The method according to claim 7 , further comprising concurrently programming a set of cells, wherein at least two cells in the set of cells are programmed to different threshold voltages.

9. A method of programming a multi-level cell (MLC) memory array comprising: deriving at least one programming vector associated with at least two specific program states, and concurrently programming a set of cells, wherein at least two cells in the set of cells are designated for programming to different threshold voltages corresponding to the at least two specific program states.

10. A multi-level cell (“MLC”) memory array programming circuit comprising: a controller adapted to map a first pair of bits from an input register to a first element of a programming vector associated with at least one specific program state.

11. The circuit according to the claim 10 , further comprising a binary input register adapted to store data to be written into an MLC array.

12. The circuit according to claim 10 , further comprising a programming vector register adapted to store a programming vector.

13. The circuit according to claim 12 , wherein each element in the programming vector corresponds to a charge storage region of an MLC in the array.

14. The circuit according to claim 13 , wherein said controller is further adapted to map a second pair of bits from said binary input register to a second element in the programming vector.

15. The circuit according to claim 10 , wherein said controller maps a pair of bits to an element of the programming vector by setting the element value to a “program” value if the pair of bits corresponds to the at least one specific program state with which the programming vector is associated.

16. The circuit according to claim 10 , wherein said controller maps a pair of bits to an element of the programming vector by setting the element value to a “do-not-program” value if the pair of bits does not correspond to the at least one specific program state with which the programming vector is associated.

17. The circuit according to claim 15 , wherein said controller causes a programming pulse to be applied to each MLC charge storage region in the array corresponding to a vector element whose value is set at a “program” value.

18. The circuit according to claim 17 , wherein said controller causes a vector element value to be se to “do-not-program” once the MLC corresponding to the element is programmed to the at least one program state with which the programming vector is associated.

19. The circuit according to claim 10 , wherein said controller is adapted to map pairs of bits from said binary input register to the elements of a second programming vector associated with a second program state and wherein mapping a pair of bits to an element of the second programming vector comprises setting the element to a “program” value if the pair of bits corresponds to the second program state with which the second vector is associated.

20. The circuit according to claim 10 , wherein the vector is associated with each of two or more specific program states.

21. The circuit according to claim 20 , wherein the two or more specific program states comprise at least a first program state and a second program state, wherein the second program state is associated with a higher threshold voltage than the first program state.

22. The circuit according to claim 21 , wherein said controller is adapted to cause concurrent program of a set of cells, wherein at least two cells in the set of cells are programmed to different threshold voltages.

23. A multi-level cell (“MLC”) memory device comprising a non-volatile memory array; and a controller adapted to map a first pair of bits from an input register to a first element of a programming vector associated with at least one specific program state.

24. The device according to the claim 23 , further comprising a binary input register adapted to store data to be written into an MLC array.

25. The device according to claim 23 , further comprising a programming vector register adapted to store a programming vector.

26. The device according to claim 25 , wherein each element in the programming vector corresponds to a charge storage region of an MLC in the array.

27. The device according to claim 26 , wherein said controller is further adapted to map a second pair of bits from said binary input register to a second element in the programming vector.

28. The device according to claim 23 , wherein said controller maps a pair of bits to an element of the programming vector by setting the element value to a “program” value if the pair of bits corresponds to the at least one specific program state with which the programming vector is associated.

29. The device according to claim 23 , wherein said controller maps a pair of bits to an element of the programming vector by setting the element value to a “do-not-program” value if the pair of bits does not correspond to the at least one specific program state with which the programming vector is associated.

30. The device according to claim 28 , wherein said controller causes a programming pulse to be applied to each MLC charge storage region in the array corresponding to a vector element whose value is set at a “program” value.

31. The device according to claim 30 , wherein said controller causes a vector element value to be se to “do-not-program” once the MLC corresponding to the element is programmed to the at least one program state with which the programming vector is associated.

32. The device according to claim 23 , wherein said controller is adapted to map pairs of bits from said binary input register to the elements of a second programming vector associated with a second program state and wherein mapping a pair of bits to an element of the second programming vector comprises setting the element to a “program” value if the pair of bits corresponds to the second program state with which the second vector is associated.

33. The device according to claim 23 , wherein the vector is associated with each of two or more specific program states.

34. The device according to claim 33 , wherein the two or more specific program states comprise at least a first program state and a second program state, wherein the second program state is associated with a higher threshold voltage than the first program state.

35. The device according to claim 34 , wherein said controller is adapted to cause concurrent program of a set of cells, wherein at least two cells in the set of cells are programmed to different threshold voltages.