Method for fabricating capacitor

1. A method for fabricating a semiconductor device, the method comprising:

forming an insulation structure over a substrate structure including contact plugs;

etching the insulation structure to form opening regions each of which has a lower opening portion having a critical dimension wider than an upper opening portion; and

forming a conductive layer contacting the contact plugs inside the opening regions,

wherein etching the bottom electrode isolation structure to form the opening regions comprises:

forming an etch barrier layer over the substrate structure;

forming the insulation structure including first to third insulation layers over the etch barrier layer, wherein the second insulation layer is interposed between the first insulation layer and the third insulation layer and has an etch selectivity ratio different from those of the first and third insulation layers;

etching the third insulation layer to form the upper opening portions each having a widened bottom critical dimension;

etching the second insulation layer and the first insulation layer in a self-aligned manner using a patterned third insulation layer as an etch barrier, the patterned third insulation layer including the upper opening portions with the widened bottom critical dimension; and

etching the etch barrier layer.

2. The method of claim 1 , wherein etching the third insulation layer comprises using an etch gas that provides an etch selectivity ratio of the third insulation layer to the second insulation layer at about 6 to 1 or above, so that a lower portion of the third insulation layer above the second insulation layer is widened relative to an upper portion of the third insulation layer.

3. The method of claim 1 , wherein etching the first insulation layer comprises using an etch gas that provides an etch selectivity ratio of the first insulation layer to the second insulation layer at about 6 to 1 or above.

4. The method of claim 1 , wherein etching the second insulation layer comprises using an etch gas that provides an etch selectivity ratio of the second insulation layer to each of the first and third insulation layers at about 1 to 1.

5. The method of claim 4 , wherein the first and third insulation layers include oxide-based materials; and the second insulation layer and the etch barrier layer each include a nitride-based material.

6. The method of claim 5 , wherein the first insulation layer includes phosphosilicate glass (PSG); the third insulation layer includes plasma enhanced tetraethyl orthosilicate (PETEOS); and the second insulation layer and the etch barrier layer each include silicon nitride.

7. The method of claim 6 , wherein etching the first insulation layer and etching the third insulation layer comprise using a mixture gas including O 2 , CHF 3 and CF 4 .

8. The method of claim 7 , wherein the O 2 , CHF 3 and CF 4 of the mixture gas have respective flow rates of about 3 sccm to 7 sccm, about 30 sccm to 50 sccm, and about 20 sccm to 60 sccm.

9. The method of claim 6 , wherein etching the second insulation layer comprises using a mixture gas including O 2 and CHF 3 .

10. The method of claim 9 , wherein the O 2 and CHF 3 of the mixture gas have respective flow rates of about 3 sccm to 7 sccm and about 30 sccm to 60 sccm.

11. The method of claim 6 , wherein etching the etch barrier layer comprises using a mixture gas including O 2 and CHF 3 .

12. The method of claim 11 , wherein the O 2 and CHF 3 of the mixture gas have respective flow rates of about 3 sccm to 7 sccm and about 30 sccm to 60 sccm.

13. The method of claim 5 , wherein the second insulation layer is formed to a thickness of about 100 Å to 300 Å.

14. A method for fabricating a capacitor, the method comprising:

forming a bottom electrode isolation structure over a substrate structure including storage node contact plugs;

etching the bottom electrode isolation structure to form opening regions each of which has a lower opening portion having a critical dimension wider than an upper opening portion; and

forming bottom electrodes contacting the storage node contact plugs inside the opening regions, respectively,

wherein etching the bottom electrode isolation structure to form the opening regions comprises:

forming an etch barrier layer over the substrate structure;

forming the bottom electrode isolation structure including first to third insulation layers over the etch barrier layer, wherein the second insulation layer is interposed between the first insulation layer and the third insulation layer and has an etch selectivity ratio different from those of the first and third insulation layers;

etching the third insulation layer to form the upper opening portions each having a widened bottom critical dimension;

etching the second insulation layer and the first insulation layer in a self-aligned manner using a patterned third insulation layer as an etch barrier, the patterned third insulation layer including the upper opening portions with the widened bottom critical dimension; and

etching the etch barrier layer.

15. The method of claim 14 , wherein etching the third insulation layer comprises using an etch gas that provides an etch selectivity ratio of the third insulation layer to the second insulation layer at about 6 to 1 or above, so that a lower portion of the third insulation layer above the second insulation layer is widened relative to an upper portion of the third insulation layer.

16. The method of claim 14 , wherein etching the first insulation layer comprises using an etch gas that provides an etch selectivity ratio of the first insulation layer to the second insulation layer at about 6 to 1 or above.

17. The method of claim 14 , wherein etching the second insulation layer comprises using an etch gas that provides an etch selectivity ratio of the second insulation layer to each of the first and third insulation layers at about 1 to 1.

18. The method of claim 17 , wherein the first and third insulation layers include oxide-based materials; and the second insulation layer and the etch barrier layer each include a nitride-based material.

19. The method of claim 18 , wherein the first insulation layer includes phosphosilicate glass (PSG); the third insulation layer includes plasma enhanced tetraethyl orthosilicate (PETEOS); and the second insulation layer and the etch barrier layer each include silicon nitride.

20. The method of claim 18 , wherein etching the first insulation layer and etching the third insulation layer comprise using a mixture gas including O 2 , CHF 3 and CF 4 .

21. The method of claim 20 , wherein the O 2 , CHF 3 and CF 4 of the mixture gas have respective flow rates of about 3 sccm to 7 sccm, about 30 sccm to 50 sccm, and about 20 sccm to 60 sccm.

22. The method of claim 18 , wherein etching the second insulation layer comprises using a mixture gas including O 2 and CHF 3 .

23. The method of claim 22 , wherein the O 2 and CHF 3 of the mixture gas have respective flow rates of about 3 sccm to 7 sccm and about 30 sccm to 60 sccm.

24. The method of claim 18 , wherein the second insulation layer is formed to a thickness of about 100 Å to 300 Å.

25. The method of claim 18 , wherein etching the etch barrier layer comprises using a mixture gas including O 2 and CHF 3 .

26. The method of claim 25 , wherein the O 2 and CHF 3 of the mixture gas have respective flow rates of about 3 sccm to 7 sccm and about 30 sccm to 60 sccm.