IP Library Granted Patent US 7,834,374
Granted Patent B2
US 7,834,374 · App. 11/708,133 · Granted Nov 16, 2010

Light emitting diode having vertical topology and method of making the same

Assignees: LG Electronics Inc.; LG Innotek Co., Ltd.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,834,374
App. No.
11/708,133
Granted
Nov 16, 2010
Kind
B2
Abstract

An LED having vertical topology and a method of making the same is capable of improving a luminous efficiency and reliability, and is also capable of achieving mass productivity. The method includes forming a semiconductor layer on a substrate; forming a first electrode on the semiconductor layer; forming a supporting layer on the first electrode; generating an acoustic stress wave at the interface between the substrate and semiconductor layer, thereby separating the substrate from the semiconductor layer; and forming a second electrode on the semiconductor layer exposed by the separation of the substrate.

Claims (50)

1. A light emitting diode (LED) having vertical topology, comprising:

a semiconductor structure comprising a plurality of semiconductor layers;

a first electrode disposed on a first surface of the semiconductor structure, the first electrode comprising a reflective electrode;

a passivation layer disposed on at least one of the first electrode and the semiconductor structure;

a connection metal layer disposed on the first electrode;

a second electrode on a second surface of the semiconductor structure;

and a supporting layer disposed on the connection metal layer,

wherein the connection metal layer comprises a first metal layer electrically connected to the first electrode, a diffusion barrier layer disposed on the first metal layer, and a second metal layer disposed on the diffusion barrier layer.

2. The LED according to claim 1 , further comprising a metal layer disposed between the passivation layer and the connection metal layer.

3. The LED according to claim 1 , wherein the plurality of semiconductor layers comprise:

an n-type semiconductor layer;

an active layer disposed on the n-type semiconductor layer; and

a p-type semiconductor layer disposed on the active layer.

4. The LED according to claim 3 , further comprising a current diffusion layer comprising an InGaN layer or an InGaN/GaN superlattice layer, on the p-type semiconductor layer.

5. The LED according to claim 1 , wherein the reflective electrode comprises Ag or Al.

6. The LED according to claim 1 , wherein the reflective electrode has a thickness of more than 100 Å.

7. The LED according to claim 1 , wherein the reflective electrode comprises a third metal layer electrically connected to the semiconductor structure; a second diffusion barrier layer disposed on the third metal layer; and a fourth metal layer disposed on the second diffusion barrier layer.

8. The LED according to claim 7 , wherein the third metal layer, the second diffusion barrier layer and the fourth metal layer are formed of a single alloy layer.

9. The LED according to claim 1 , wherein the first metal layer, the diffusion barrier layer and the second metal layer are formed of a single alloy layer.

10. The LED according to claim 1 , wherein the first electrode further comprises a transparent electrode.

11. The LED according to claim 1 , further comprising a light-extraction structure on the second surface of the semiconductor structure.

12. The LED according to claim 11 , wherein the light-extraction structure comprises a photonic crystal structure.

13. The LED according to claim 12 , wherein the photonic crystal structure has a period of 0.2 to 2 μm.

14. The LED according to claim 12 , wherein the photonic crystal structure comprises a pattern having a six-fold(60°) or twelve-fold(30°) rotational symmetry.

15. The LED according to claim 14 , wherein the pattern comprises a unit cell having 19 holes, and wherein the unit cell shares 6 of 19 holes with adjacent unit cells.

16. The LED according to claim 15 , wherein the 19 holes have a distribution having 1 hole in the center of the cell, 6 holes therearound, arranged at the same intervals, and 12 holes arranged at the same intervals around the 6 holes.

17. The LED according to claim 12 , wherein the photonic crystal structure has a translational symmetry.

18. The LED according to claim 1 , wherein the supporting layer comprises a side rim protion for supporting a lateral side of the semiconductor structure, via contact with the connection metal layer.

19. The LED according to claim 1 , wherein the passivation layer comprises at least one of silicon dioxide (SiO 2 ), photoresist (PR), SOG and polyimide.

20. A light emitting diode (LED) having vertical topology, comprising:

a semiconductor structure comprising a plurality of semiconductor layers;

a first electrode disposed on a first surface of the semiconductor structure and comprising at least two layers;

a light-extraction structure on at least a portion of a second surface of the semiconductor structure, the light-extraction structure including a first photonic crystal structure that includes randomly positioned unit structures, wherein the light-extraction structure reflects a second photonic crystal structure including periodically positioned unit structures, and wherein the distance between the periodically positioned unit structures substantially equals the average distance between the randomly positioned unit structures;

a second electrode disposed on the second surface of the semiconductor structure; and

a supporting layer disposed on the first electrode.

21. The LED according to claim 20 , further comprising:

a current diffusion layer between the first surface of the semiconductor structure and the first electrode.

22. The LED according to claim 20 , wherein the light-extraction structure comprises a photonic crystal structure having a plurality of holes, wherein the diameter of the hole is in the range of 0.1 A to 0.9 A (where, A is the period of the photonic crystal structure), and the depth of the hole is in the range of 0.1 μm to 5 μm.

23. The LED according to claim 20 , further comprising:

a current diffusion layer comprising an InGaN layer or an InGaN/GaN superlattice layer between the first surface of the semiconductor structure and the first electrode.

24. The LED according to claim 1 , wherein the connection metal layer contacts the passivation layer.

25. The LED according to claim 1 , wherein the first electrode is formed integrally with the connection metal layer.

26. The LED according to claim 1 , wherein the connection metal layer comprises a seed metal for formation of the supporting layer or a bonding metal for attaching the supporting layer.

27. The LED according to claim 1 , wherein the first electrode comprises a transparent conductive oxide layer.

28. The LED according to claim 20 , further comprising a connection metal layer disposed between the first electrode and the supporting layer.

29. The LED according to claim 28 , wherein the connection metal layer comprises a seed metal for formation of the supporting layer or a bonding metal for attaching the supporting layer.

30. The LED according to claim 28 , wherein the first electrode is formed integrally with the connection metal layer.

31. The LED according to claim 20 , wherein the supporting layer comprises a side rim portion for supporting a lateral side of the semiconductor structure.

32. The LED according to claim 20 , wherein the first electrode comprises a transparent conductive oxide layer.

33. The LED according to claim 1 , wherein the connection metal layer directly contacts and is disposed between the first electrode and the supporting layer.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 25, 2025
From: LG ELECTRONICS INC.
To: SUZHOU LEKIN SEMICONDUCTOR CO., LTD.
Reel/Frame 072529/0173 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2021
From: LG INNOTEK CO., LTD.
To: SUZHOU LEKIN SEMICONDUCTOR CO., LTD.
Reel/Frame 056366/0335 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 14, 2007
From: JANG, JUN HO; CHOI, JAE WAN; BAE, DUK KYE; CHO, HYUN KYONG; PARK, JONG KOOK; KIM, SUN JUNG; LEE, JEONG SOO
To: LG ELECTRONICS INC.; LG INNOTEK CO., LTD
Reel/Frame 019459/0490 →
Priority Claims (3)
KR 10-2006-0057033 · Jun 23, 2006 · national
KR 10-2006-0093465 · Sep 26, 2006 · national
KR 10-2006-0093574 · Sep 26, 2006 · national
Continuity (1)
Related Publication 20070295952A1 · Dec 27, 2007