Low power decision feedback equalization (DFE) through applying DFE data to input data in a data latch
Low power decision feedback equalization (DFE) through applying DFE data to input data in a data latch is disclosed. In one embodiment, a decision feedback equalization (DFE) system to remove a post cursor intersymbol interference (ISI) through feeding back previous data scaled with adaptive weights to the DFE system, with each slice of the DFE system may include a first set of decision feedback digital to analog converters (DACs) to generate a first DFE data obtained through the feeding back the previous data scaled with the adaptive weights and a first data latch to generate an output data of the each slice through applying the first DFE data to an input data of the each slice in the first data latch to remove a first delay caused by performing the applying the first DFE data to the input data of the each slice outside of the first data latch.
1. A decision feedback equalization (DFE) system to remove a post cursor intersymbol interference (ISI), with each slice of the DFE system, comprising:
a first set of decision feedback digital to analog converters (DACs) to generate a first DFE data through applying adaptive weights to previous data;
a first data latch to generate an output data of the each slice through applying the first DFE data to an input data of the each slice in the first data latch to remove a first delay caused by performing the applying the first DFE data to the input data of the each slice outside of the first data latch;
a second set of decision feedback DACs to generate a second DFE data through applying the adaptive weights and a negative threshold value to the previous data;
a second data latch to generate a negative error data of the each slice through applying the second DFE data to the input data of the each slice in the second data latch to remove a second delay caused by performing the applying the second DFE data to the input data outside of the second data latch;
a third set of decision feedback DACs to generate a third DFE data through applying the adaptive weights and a positive threshold value to the previous data;
a third data latch to generate a positive error data of the each slice through applying the third DFE data from the input data of the each slice in the third data latch to remove a third delay caused by performing the applying the third DFE data to the input data outside of the third data latch;
a clock and a data recovery circuit to generate an optimum location to sample the input data based on the output data, the negative error data, and the positive error data;
an adaptor circuit to adjust the adaptive weights based on the output data, the negative error data, and the positive error data, wherein the adaptive weights are amounts of ISI injects of the previous data to the input data; and
a phase interpolator to adjust a timing of a clock based on a voltage controlled oscillator (VCO), wherein the timing obtained through the clock and the data recovery circuit controls sampling of the input data,
wherein an average power consumption of the DFE system is lowered by 2 to 3 mili-watts per each of the first data latch, the second data latch, and the third data latch when compared to a DFE system with additional circuits to perform the applying the first DFE data, the second DFE data, and the third DFE data to the input data.
2. The DFE system of claim 1 wherein the input data is at least one of a pseudo-differential input to reject a DC common-mode voltage and a fully-differential input to reject a DC common-mode voltage and a dynamic common-mode voltage.
3. The DFE system of claim 1 wherein the DFE system is comprised of four parallel DFE circuits with each of the four parallel DFE circuits is based on the each slice to recover the input data in 6.4 giga-bits per second (GB/s) with the VCO of the each slice of the four parallel circuits_to have a 1.6 GHz ring oscillator.
4. The DFE system of claim 3 wherein the timing of the clock is delayed by one tap clock rate between any two adjacent circuits of the four parallel DFE circuits.
5. A method of a decision feedback equalization (DFE) system, comprising:
applying a DFE data to a differential input data during a clocking of a data latch through directly coupling decision feedback digital to analog converters generating the DFE data to the data latch to remove a delay due to having the applying the DFE data to the differential input data outside of the data latch; and
generating an output data obtained through the applying the decision feedback equalization data to the differential input data to remove an intersymbol interference associated with the differential input data;
generating an error data through applying a threshold data and a previous data weighed by ISI injects associated with previous data to the differential input data; and
locating an optimal location to sample the differential input data using a clock and data recovery circuit based on the differential input data and the error data,
wherein DFE digital to analog converters (DACs) generating the DFE data are shared by the data latch generating the output data and another data latch generating the error data such that a power consumption of the DFE system is decreased by at least 20 percent.
6. The method of claim 5 wherein a die space of the DFE system is reduced by at least 5% by removing at least 50% of the DFE DACs of the DFE system.
7. A decision feedback equalization (DFE) system to remove a post cursor intersymbol interference (ISI), with each slice of the DFE system, comprising:
a first set of decision feedback digital to analog converters (DACs) to generate a first DFE data through applying adaptive weights to previous data;
a first data latch to generate an output data of the each slice through applying the first DFE data to an input data of the each slice in the first data latch to remove a first delay caused by performing the applying the first DFE data to the input data of the each slice outside of the first data latch;
a second set of decision feedback DACs to generate a second DFE data through applying the adaptive weights and a negative threshold value to the previous data;
a second data latch to generate a negative error data of the each slice through applying the second DFE data to the input data of the each slice in the second data latch to remove a second delay caused by performing the applying the second DFE data to the input data outside of the second data latch;
a third set of decision feedback DACs to generate a third DFE data through applying the adaptive weights and a positive threshold value to the previous data;
a third data latch to generate a positive error data of the each slice through applying the third DFE data from the input data of the each slice in the third data latch to remove a third delay caused by performing the applying the third DFE data to the input data outside of the third data latch;
a clock and a data recovery circuit to generate an optimum location to sample the input data based on the output data, the negative error data, and the positive error data;
an adaptor circuit to adjust the adaptive weights based on the output data, the negative error data, and the positive error data, wherein the adaptive weights are amounts of ISI injects of the previous data to the input data; and
a phase interpolator to adjust a timing of a clock based on a voltage controlled oscillator (VCO), wherein the timing obtained through the clock and the data recovery circuit controls sampling of the input data,
wherein an average power consumption of the DFE system is lowered by 2 to 3 mili-watts per each of the first data latch, the second data latch, and the third data latch when compared to a DFE system with additional circuits to perform the applying the first DFE data, the second DFE data, and the third DFE data to the input data,
wherein the DFE system is comprised of four parallel DFE circuits with each of the four parallel DFE circuits is based on the each slice to recover the input data in 6.4 giga-bits per second (GB/s) with the VCO of the each slice of the four parallel circuits to have a 1.6 GHz ring oscillator.
8. The DFE system of claim 7 wherein the input data is at least one of a pseudo-differential input to reject a DC common-mode voltage and a fully-differential input to reject a DC common-mode voltage and a dynamic common-mode voltage.
9. The DFE system of claim 7 wherein the timing of the clock is delayed by one tap clock rate between any two adjacent circuits of the four parallel DFE circuits.
10. A decision feedback equalization (DFE) system to remove a post cursor intersymbol interference (ISI), with each slice of the DFE system, comprising:
a first set of decision feedback digital to analog converters (DACs) to generate a first DFE data through applying adaptive weights to previous data;
a first data latch to generate an output data of the each slice through applying the first DFE data to an input data of the each slice in the first data latch to remove a first delay caused by performing the applying the first DFE data to the input data of the each slice outside of the first data latch;
a second set of decision feedback DACs to generate a second DFE data through applying the adaptive weights and a negative threshold value to the previous data;
a second data latch to generate a negative error data of the each slice through applying the second DFE data to the input data of the each slice in the second data latch to remove a second delay caused by performing the applying the second DFE data to the input data outside of the second data latch;
a third set of decision feedback DACs to generate a third DFE data through applying the adaptive weights and a positive threshold value to the previous data;
a third data latch to generate a positive error data of the each slice through applying the third DFE data from the input data of the each slice in the third data latch to remove a third delay caused by performing the applying the third DFE data to the input data outside of the third data latch;
a clock and a data recovery circuit to generate an optimum location to sample the input data based on the output data, the negative error data, and the positive error data;
an adaptor circuit to adjust the adaptive weights based on the output data, the negative error data, and the positive error data, wherein the adaptive weights are amounts of ISI injects of the previous data to the input data; and
a phase interpolator to adjust a timing of a clock based on a voltage controlled oscillator (VCO), wherein the timing obtained through the clock and the data recovery circuit controls sampling of the input data,
wherein an average power consumption of the DFE system is lowered by 2 to 3 mili-watts per each of the first data latch, the second data latch, and the third data latch when compared to a DFE system with additional circuits to perform the applying the first DFE data, the second DFE data, and the third DFE data to the input data,
wherein the DFE system is comprised of four parallel DFE circuits with each of the four parallel DFE circuits is based on the each slice to recover the input data in 6.4 giga-bits per second (GB/s) with the VCO of the each slice of the four parallel circuits to have a 1.6 GHz ring oscillator, and
wherein the timing of the clock is delayed by one tap clock rate between any two adjacent circuits of the four parallel DFE circuits.
11. The DFE system of claim 10 wherein the input data is at least one of a pseudo-differential input to reject a DC common-mode voltage and a fully-differential input to reject a DC common-mode voltage and a dynamic common-mode voltage.
12. A method of a decision feedback equalization (DFE) system, comprising:
applying a DFE data to a differential input data during a clocking of a data latch through directly coupling decision feedback digital to analog converters generating the DFE data to the data latch to remove a delay due to having the applying the DFE data to the differential input data outside of the data latch;
generating an output data obtained through the applying the decision feedback equalization data to the differential input data to remove an intersymbol interference associated with the differential input data;
generating an error data through applying a threshold data and a previous data weighed by ISI injects associated with previous data to the differential input data; and
locating an optimal location to sample the differential input data using a clock and data recovery circuit based on the differential input data and the error data,
wherein DFE digital to analog converters (DACs) generating the DFE data are shared by the data latch generating the output data and another data latch generating the error data such that a power consumption of the DFE system is decreased by at least 20 percent, and
wherein a die space of the DFE system is reduced by at least 5% by removing at least 50% of the DFE DACs of the DFE system.