Test mode enable circuit

1. A test mode enable circuit for putting a device in a test mode comprising:

a serial-to-parallel shift register including a plurality of memory circuits, each of which is initialized to a first voltage level by a reset signal, the shift register receiving and converting a control signal in serial form to control data in parallel form, the control signal comprising a plurality of digital bits, each of which has the first voltage level or a second voltage level and being shifted through the shift register from a first memory circuit of the plurality of memory circuits to a second memory circuit of the plurality of memory circuits to produce the control data, the first memory circuit corresponding to a least significant bit of the control data, the second memory circuit corresponding to a most significant bit of the control data;

a decoder circuit for receiving the control data from the shift register and for outputting a test mode enable signal that puts the device in the test mode when the most significant bit of the control data has the second voltage level and at least one of other bits of the control data has a first predetermined voltage level; and

a gate circuit for receiving the test mode enable signal from the decoder circuit, wherein

the gate circuit passes the test mode enable signal to the device, when at least one of the bits of the control signal and the reset signal has a second predetermined voltage level.

2. The enable circuit according to claim 1 , wherein

the decoder circuit outputs the test mode enable signal when the most significant bit of the control data has the second voltage level and the at least one of other bits of the control data has the first voltage level.

3. The enable circuit according to claim 1 , wherein

the decoder circuit outputs the test mode enable signal, when each of the most and least significant bits of the control data has the second voltage level and at least one of the other bits of the control data has the first voltage level.

4. The enable circuit according to claim 1 , wherein

the decoder circuit decodes the bits, excluding the most significant bit and the at least one of other bits, of the control data, into a test mode selection signal that determines which test mode the device is put in.

5. The enable circuit according to claim 1 , wherein

the plurality of memory circuits of the shift register is initialized to the first level by the reset signal having the first level, and

the gate circuit outputs the test mode enable signal, when each of the control signal and the reset signal has the second voltage level.

6. The enable circuit according to claim 1 , further comprising

an OR logic gate, wherein

the shift register has a reset input for receiving the reset signal,

an output of the OR logic gate is connected to the reset input of the shift register,

the reset signal is fed to a first input of the OR logic gate, and

a power-on reset signal is fed to a second input of the OR logic gate.

7. The enable circuit according to claim 1 , wherein

the decoder circuit outputs the test mode enable signal only when the most significant bit of the control data has the second voltage level and at least one of other bits of the control data has the first predetermined voltage, and

the gate circuit passes the test mode enable signal to the device only when the at least one of the bits of the control signal and the reset signal have the second predetermined voltage level.