Semiconductor device
View Patent ↗A semiconductor device, which exhibits an increased design flexibility for a capacitor element, and can be manufactured with simple method, is provided. A semiconductor device 100 includes: a silicon substrate 101 ; an interlayer film 103 provided on the silicon substrate 101 ; a multiple-layered interconnect embedded in the interlayer film 103 ; a flip-chip pad 111 , provided so as to be opposite to an upper surface of an uppermost layer interconnect 105 in the multiple-layered interconnect and having a solder ball 113 for an external coupling mounted thereon; and a capacitance film 109 provided between said uppermost layer interconnect 105 and the flip-chip pad 111 . Such semiconductor device 100 includes the flip-chip pad 111 composed of an uppermost layer interconnect 105 , a capacitive film 109 and a capacitor element 110.
1. A semiconductor device, comprising:
a semiconductor substrate;
an insulating interlayer on said semiconductor substrate;
a multiple-layered interconnect embedded in said insulating interlayer;
an electrode pad provided so as to be opposite an upper surface of an uppermost layer of said multiple-layered interconnect, said electrode pad having a bump electrode for an external coupling mounted thereon; and
a first insulating film interposed between said uppermost layer of said multiple-layered interconnect and said electrode pad, said first insulating film consisting of a single material contacting an entirety of an uppermost surface of said uppermost layer of said multiple-layered interconnect, said first insulating film covering an upper portion of said insulating interlayer and having a concave portion provided in a region opposite said uppermost surface of said uppermost layer of said multiple-layered interconnect, thereby forming a capacitor element with said uppermost layer of said multiple-layered interconnect and said electrode pad,
wherein a thickness of said first insulating film is reduced in the region where said concave portion is formed, and a capacitance is formed in the region of said first insulating film having the reduced thickness.
2. The semiconductor device according to claim 1 , wherein said electrode pad is provided so as to cover an interior wall of said concave portion and to extend to outside of said concave portion.
3. The semiconductor device according to claim 1 , wherein said multiple-layered interconnect comprises a first layer selected from the group consisting of Al, Cu and an alloy thereof and a second layer selected from the group consisting of Ti, TiN, TiW, Ta and TaN.
4. The semiconductor device according to claim 1 , wherein said uppermost surface of said uppermost layer of said multiple-layered interconnect is substantially coplanar with an uppermost surface of said insulating interlayer.
5. The semiconductor device according to claim 1 , wherein said bump electrode is arranged to overlap said electrode pad so that said electrode pad is behind said bump electrode in plan view of the device.
6. The semiconductor device according to claim 1 , wherein said bump electrode is arranged to overlap a region of said capacitor element so that said capacitor element is behind said bump electrode in plan view of the device.
7. The semiconductor device according to claim 1 , wherein said uppermost layer of said multiple-layered interconnect is embedded in a second concave portion provided in said insulating interlayer, and said first insulating film covers on a boundary between said uppermost layer of said multiple-layered interconnect and said insulating interlayer in plan view, thereby is stacked on said uppermost layer of said multiple-layered interconnect and said insulating interlayer.
8. The semiconductor device according to claim 7 , wherein said uppermost layer of said multiple-layered interconnect is formed so as to fill an upper portion of said second concave portion provided in said insulating interlayer.