Transistors and manufacturing methods thereof
View Patent ↗Transistors and manufacturing methods thereof are disclosed. An example transistor includes a semiconductor substrate divided into device isolation regions and a device active region. The example transistor includes a gate insulating film formed in the active region of the semiconductor substrate, a gate formed on the gate insulating film, a channel region formed in the semiconductor substrate and overlapping the gate, and LDD regions formed in the semiconductor substrate and at both sides of the gate, centering the gate. In addition, the example transistor includes source and drain regions formed under the LDD regions, offset regions formed in the semiconductor substrate and between the channel region and LDD regions, and gate spacers formed at both sidewalls of the gate.
1. A transistor comprising:
a semiconductor substrate having device isolation regions and a device active region;
a gate insulating film in the active region of the semiconductor substrate;
a gate on the gate insulating film;
a channel region in the semiconductor substrate under the gate;
LDD regions in the active regions, under the gate insulating film in the semiconductor substrate and having substantially rectangular cross-sections and a lowermost surface substantially coplanar with an uppermost surface of the channel region;
source and drain regions under the LDD regions;
offset regions in the semiconductor substrate adjacent to the LDD regions having substantially rectangular cross-sections and uppermost and lowermost surfaces coplanar with uppermost and lowermost surfaces of the LDD regions; and
gate spacers at sidewalls of the gate.
2. The transistor of claim 1 , wherein the offset regions include N-type impurity ions and the LDD regions include P-type impurity ions.
3. The transistor of claim 1 , wherein the offset regions include P-type impurity ions and the LDD regions include N-type impurity ions.
4. A transistor comprising:
a semiconductor substrate having device isolation regions and a device active region;
a gate insulating film in the active region of the semiconductor substrate;
a gate on the gate insulating film;
LDD) regions in the active regions, under the gate insulating film and uncovered by the gate, substantially rectangular cross-sections;
source and drain regions under the LDD regions;
offset regions in the semiconductor substrate adjacent to the LDD regions, having substantially rectangular cross-sections and uppermost and lowermost surfaces coplanar with uppermost and lowermost surfaces of the LDD regions; and
gate spacers at sidewalk of the gate.
5. The transistor of claim 4 , wherein the offset regions include N-type impurity ions and the LDD regions include P-type impurity ions.
6. The transistor of claim 4 , wherein the offset regions include P-type impurity ions and the LDD regions include N-type impurity ions.
7. The transistor of claim 1 , wherein the LDD regions are under opposite end of the gate insulating film.
8. The transistor of claim 1 , wherein the gate has a bottom surface coplanar with a bottom of the LDD regions.
9. The transistor of claim 1 ., wherein the LDD regions are not covered by the gate.
10. The transistor of claim 4 , wherein the gate insulating film comprises an oxide film.
11. The transistor of claim 4 , wherein the gate insulating film has a thickness of 50Å to 200Å.
12. The transistor of claim 4 , wherein the gate comprises poly-silicon.
13. The transistor of claim 4 , further comprising a channel region between the offset regions.
14. The transistor of claim 4 , wherein the channel region comprises epitaxial silicon.
15. The transistor of claim 4 , wherein the LDD regions are under opposite end of the gate insulating film.
16. The transistor of claim 1 , wherein the gate insulating film comprises an oxide film.
17. The transistor of claim 1 , where in the gate insulating film has a thickness of 50Å to 200Å.