Programmable address space built-in self test (BIST) device and method for fault detection
View Patent ↗A built-in self-test (BIST) circuit for testing addressable locations can include a BIST generator ( 202 ) that can generate test addresses for testing each addressable location. Defective addresses can be stored in a fault address store ( 216 ). An address range selector circuit ( 230 ) can limit the range of addresses generated by an address generator ( 234 ). Once defective addresses for a first range have been detected, an address range selector circuit ( 230 ) can test another range. An entire address range can thus be tested regardless of the depth of a fault address store ( 216 ).
1. An integrated circuit device, comprising:
a main section comprising a plurality of locations, each accessed according to a unique address;
an address range selector that provides at least one programmable address limit value;
a test address generator that generates a plurality of addresses in a test mode, the plurality of addresses being less than all the addresses of the main section and being defined according to the at least one programmable address limit value; and
a fault address store having a plurality of storage locations for storing addresses of faulty locations in the main section.
2. The integrated circuit device of claim 1 , wherein:
the main section comprises a content addressable memory (CAM) device comprising a plurality of CAM locations, each for storing a data value for comparison to a search key.
3. The integrated circuit device circuit of claim 2 , wherein:
each CAM location comprises a plurality of CAM cells having compare circuitry for comparing at least one search key bit to a stored data bit.
4. The integrated circuit device circuit of claim 1 , wherein:
the address range selector provides a low limit address and a high limit address; and
the test address generator generates test addresses having a range established by a low limit address and a high limit address.
5. The integrated circuit device of claim 1 , wherein: the fault address store comprises a first-in-first-out (FIFO) memory circuit.
6. The integrated circuit device of claim 5 , wherein:
the number of locations in the main section is no less than 32 k (32×1024); and
the number of storage locations in the fault address store is no more than eight.
7. An integrated circuit device, comprising:
a tested circuit comprising a plurality of addressable locations covering a total address range;
a range setting circuit that stores at least one programmable address corresponding to one of the addressable locations;
an address generator that generates a sequence of test addresses covering a test address range of addresses in a test mode, the test address range covering less than the total address range; and
a fault address store, comprising a first-in-first-out (FIFO) circuit, that stores addresses of addressable locations determined to be faulty in response to the application of at least a test address to access an addressable location.
8. The integrated circuit device of claim 7 , wherein:
the at least one programmable address includes a start address and an end address; and
the test address range is defined by the start address and end address.
9. The integrated circuit device of claim 7 , further including:
a data generator that outputs test data in parallel to test addresses in the test mode.
10. The integrated circuit device claim 9 , further including:
a test algorithm selector coupled to the address generator that determines at least the order of test addresses of the test address range in the test mode.
11. The integrated circuit device claim 7 , wherein:
the tested circuit comprises a circuit selected from the group consisting of: a binary content addressable memory (CAM) array, a ternary CAM array, and a pseudo-ternary CAM array.
12. A method of self-testing an integrated circuit, comprising:
(a) storing at least one address range value;
(b) accessing a plurality of storage locations of a tested portion of the integrated circuit (IC) according to a range of test addresses determined by the at least one address range value, the range of test addresses being less than all storage locations of the tested portion; and
(c) storing the address of storage locations within the range of test addresses determined to be faulty by at least the application of a test address.
13. The method of claim 12 , wherein:
storing at least one range address value includes storing a start address and an end address; and
the range of test addresses is bounded by the start address and end address.
14. The method of claim 12 , further including:
outputting the addresses of faulty locations; and
repeating steps (a) through (c) with a different at least one address range value.
15. The method of claim 14 , wherein:
repeating step (c) includes
accessing a second plurality of storage locations of the tested portion of the IC according to a second range of test addresses that does not overlap the previous range of test addresses.
16. The method of claim 12 , wherein:
accessing the plurality of storage locations includes accessing entries of a content addressable memory (CAM) array, each of which stores a data value for comparison to a search key value.
17. The method of claim 16 , wherein:
each CAM entry comprises a plurality of CAM cells, each of which compares at least one stored bit value to a search key value.