IP Library Granted Patent US 7,871,924
Granted Patent B2
US 7,871,924 · App. 11/714,886 · Granted Jan 18, 2011

Semiconductor device having copper wiring

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Quick Facts
Patent No.
US 7,871,924
App. No.
11/714,886
Granted
Jan 18, 2011
Kind
B2
Abstract

A first interlayer insulating film made of insulting material is formed over an underlying substrate. A via hole is formed through the first interlayer insulating film. A conductive plug made of copper or alloy mainly consisting of copper is filled in the via hole. A second interlayer insulating film made of insulating material is formed over the first interlayer insulating film. A wiring groove is formed in the second interlayer insulating film, passing over the conductive plug and exposing the upper surface of the conductive plug. A wiring made of copper or alloy mainly consisting of copper is filled in the wiring groove. The total atom concentration of carbon, oxygen, nitrogen, sulfur and chlorine in the conductive plug is lower than the total atom concentration of carbon, oxygen, nitrogen, sulfur and chlorine in the wiring.

Claims (14)

1. A semiconductor manufacture method comprising steps of:

(a) forming a first interlayer insulating film made of insulating material over an underlying substrate;

(b) forming a via hole through the first interlayer insulating film;

(c) filling a conductive plug made of copper or alloy containing mainly copper in the via hole by a plating method;

(d) forming a second interlayer insulating film made of insulating material over the first interlayer insulating film with the conductive plug being filled in;

(e) forming a wiring groove in the second interlayer insulating film, the wiring groove exposing an upper surface of the conductive plug; and

(f) filling a wiring made of copper or alloy containing mainly copper in the wiring groove by a plating method using plating solution different from plating solution to be used at the step (c) in a total atom concentration of carbon, oxygen, nitrogen, sulfur and chlorine.

2. A semiconductor manufacture method according to claim 1 , wherein a total atom concentration of carbon, oxygen, nitrogen, sulfur and chlorine in the plating solution used at the step (f) is higher than a total atom concentration of carbon, oxygen, nitrogen, sulfur and chlorine used at the step (c).

3. The semiconductor manufacture method according to claim 2 , wherein the plating solutions used at the steps (c) and (f) are selected in such a manner that the total atom concentration of carbon, oxygen, nitrogen, sulfur and chlorine in the conductive plug becomes equal to or lower than one tenth of the total atom concentration of carbon, oxygen, nitrogen, sulfur and chlorine in the wiring.

4. The semiconductor manufacture method according to claim 2 , wherein the plating solutions used at the steps (c) and (f) are selected in such a manner that the total atom concentration of the conductive plug becomes lower than 1×10 19 cm −3 and the total atom concentration of the wiring becomes higher than 1×10 19 cm −3 .

5. The semiconductor manufacture method according to claim 1 , wherein the plating solutions used at the steps (c) and (f) are selected in such a manner that the total atom concentration of carbon, oxygen, nitrogen, sulfur and chlorine in the conductive plug becomes equal to or lower than one tenth of the total atom concentration of carbon, oxygen, nitrogen, sulfur and chlorine in the wiring.

6. The semiconductor manufacture method according to claim 5 , wherein the plating solutions used at the steps (c) and (f) are selected in such a manner that the total atom concentration of the conductive plug becomes lower than 1×10 19 cm −3 and the total atom concentration of the wiring becomes higher than 1×10 19 cm −3 .

7. The semiconductor manufacture method according to claim 1 , wherein the plating solutions used at the steps (c) and (f) are selected in such a manner that the total atom concentration of the conductive plug becomes lower than 1×10 19 cm −3 , and the total atom concentration of the wiring becomes higher than 1×10 19 cm −3 .

8. The semiconductor manufacture method according to claim 1 , wherein the plating solutions used at the steps (c) and (f) are selected in such a manner that a purity of copper in the conductive plug becomes different from a purity of copper in the wiring.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
MERGER Recorded May 24, 2023
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU LIMITED
Reel/Frame 064221/0545 →
CHANGE OF NAME AND CHANGE OF ADDRESS Recorded Jul 16, 2020
From: AIZU FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053481/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: AIZU FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053209/0468 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
CHANGE OF NAME Recorded Jul 9, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024651/0744 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021976/0089 →