IP Library Granted Patent US 7,870,358
Granted Patent B2
US 7,870,358 · App. 11/715,680 · Granted Jan 11, 2011

Zero-penalty RAID controller memory leak detection and isolation method and system utilizing sequence numbers

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Quick Facts
Patent No.
US 7,870,358
App. No.
11/715,680
Granted
Jan 11, 2011
Kind
B2
Abstract

A method and system for detecting and isolating memory leak in RAID controllers utilizing sequence numbers. The system monitors whether the count of un-freed memory blocks for a sequence number (SN) zone (after a start-of-day SOD operation, but smaller than the current sequence number zone) is not eventually decremented to zero. The memory leak can be detected when un-freed memory blocks exist and follow a similar pattern with respect to all other adjacent SN zones. The detected memory leak can be isolated utilizing shell commands, task information, caller information, sequence number, memory allocation size and a pointer to the next allocated memory block.

Claims (73)

1. A method for detecting and isolating a plurality of memory leak blocks using a sequence number, comprising:

utilizing a sequence number for indicating an order of memory allocation in a data-processing system, wherein said sequence number comprises a plurality of unsigned integers with an initial value of zero;

dividing a memory into a plurality of sequence number zones and thereafter monitoring a count of a plurality of un-freed memory blocks after a finish of a start-of-day (SOD) operation;

detecting said plurality of memory leak blocks when said count of said plurality of un-freed memory blocks for sequence number zones after said finish of said SOD operation, but smaller than a current sequence number zone, is not eventually decremented to zero, in order to thereby detect and isolate a plurality of memory leak blocks associated with said data-processing system; and

instantiating a plurality of global data structures by allocating memory in said data-processing system prior to using said sequence number for indicating said order of memory allocation in said data-processing system.

2. The method of claim 1 further comprising:

isolating said plurality of memory leak blocks utilizing shell commands, task information, caller information, sequence number information, memory allocation size and a pointer to a next allocation memory block; and

performing an optimization and a performance tuning operation with respect to said data-processing system utilizing a compiler directive mechanism.

3. The method of claim 1 further comprising incrementing said sequence number in response to instantiating said plurality of global data structures.

4. The method of claim 2 wherein performing said optimization and said performance tuning operation with respect to said data-processing system using said compiler directive mechanism, further comprises:

utilizing said compiler directive mechanism to enable/disable a memory leak detection and an isolation algorithm on a work-as-needed basis;

utilizing a smaller size variable for said sequence number;

defining said plurality of sequence number zones based on debug needs; and

combining said optimization and said performance tuning operation with at least one other memory leak detection and isolation operation.

5. The method of claim 1 further comprising:

instantiating a plurality of global data structures by allocating memory in said data-processing system prior to using said sequence number for indicating said order of memory allocation in said data-processing system;

isolating said plurality of memory leak blocks utilizing shell commands, task information, caller information, sequence number information, memory allocation size and a pointer to a next allocation memory block; and

performing an optimization and a performance tuning operation with respect to said data-processing system utilizing a compiler directive mechanism.

6. The method of claim 5 wherein performing said optimization and said performance tuning operation with respect to said data-processing system using said compiler directive mechanism, further comprises:

utilizing said compiler directive mechanism to enable/disable a memory leak detection and an isolation algorithm on a work-as-needed basis;

utilizing a smaller size variable for said sequence number;

defining said plurality of sequence number zones based on debug needs; and

combining said optimization and said performance tuning operation with at least one other memory leak detection and isolation operation.

7. The method of clam 5 further comprising incrementing said sequence number in response to instantiating said plurality of global data structures.

8. The method of claim 1 further comprising:

instantiating a plurality of global data structures by allocating memory in said data-processing system prior to using said sequence number for indicating said order of memory allocation in said data-processing system;

incrementing said sequence number in response to instantiating said plurality of global data structures;

isolating said plurality of memory leak blocks utilizing shell commands, task information, caller information, sequence number information, memory allocation size and a pointer to a next allocation memory block; and

performing an optimization and a performance tuning operation with respect to said data-processing system utilizing a compiler directive mechanism, wherein performing said optimization and said performance tuning operation with respect to said data-processing system using said compiler directive mechanism, further comprises:

utilizing said compiler directive mechanism to enable/disable a memory leak detection and an isolation algorithm on a work-as-needed basis;

utilizing a smaller size variable for said sequence number;

defining said plurality of sequence number zones based on debug needs; and

combining said optimization and said performance tuning operation with at least one other memory leak detection and isolation operation.

9. A method for detecting and isolating a plurality of memory leak blocks using a sequence number, comprising:

instantiating a plurality of global data structures by allocating memory in a data-processing system prior to using said sequence number for indicating an order of memory allocation in said data-processing system,

incrementing said sequence number in response to instantiating said plurality of global data structures;

utilizing said sequence number for indicating an order of memory allocation in said data-processing system, wherein said sequence number comprises a plurality of unsigned integers with an initial value of zero;

dividing a memory into a plurality of sequence number zones and thereafter monitoring a count of a plurality of un-freed memory blocks after a finish of a start-of-day (SOD) operation; and

detecting said plurality of memory leak blocks when said count of said plurality of un-freed memory blocks for sequence number zones after said finish of said SOD operation, but smaller than a current sequence number zone, is not eventually decremented to zero, in order to thereby detect and isolate a plurality of memory leak blocks associated with said data-processing system.

10. The method of claim 9 further comprising:

isolating said plurality of memory leak blocks utilizing shell commands, task information, caller information, sequence number information, memory allocation size and a pointer to a next allocation memory block; and

performing an optimization and a performance tuning operation with respect to said data-processing system utilizing a compiler directive mechanism.

11. The method of claim 9 wherein performing said optimization and said performance tuning operation with respect to said data-processing system using said compiler directive mechanism, further comprises:

utilizing said compiler directive mechanism to enable/disable a memory leak detection and an isolation algorithm on a work-as-needed basis;

utilizing a smaller size variable for said sequence number;

defining said plurality of sequence number zones based on debug needs; and

combining said optimization and said performance tuning operation with at least one other memory leak detection and isolation operation.

12. A computer-implemented system for detecting and isolating a plurality of memory leak blocks using a sequence number, said system comprising:

a data-processing apparatus;

a module executed by said data-processing apparatus, said module and said data-processing apparatus being operable in combination with one another to:

utilize a sequence number for indicating an order of memory allocation in said data-processing system, wherein said sequence number comprises a plurality of unsigned integers with an initial value of zero;

divide a memory into a plurality of sequence number zones and thereafter monitoring a count of a plurality of un-freed memory blocks after a finish of a start-of-day (SOD) operation;

detect said plurality of memory leak blocks when said count of said plurality of un-freed memory blocks for sequence number zones after said finish of said SOD operation, but smaller than a current sequence number zone, is not eventually decremented to zero, in order to thereby detect and isolate a plurality of memory leak blocks associated with said data-processing system; and

instantiate a plurality of global data structures by allocating memory in said data-processing system prior to using said sequence number for indicating said order of memory allocation in said data-processing system.

13. The system of claim 12 wherein said data-processing apparatus and said module are further operable in combination with one another to:

isolate said plurality of memory leak blocks utilizing shell commands, task information, caller information, sequence number information, memory allocation size and a pointer to a next allocation memory block; and

perform an optimization and a performance tuning operation with respect to said data-processing system utilizing a compiler directive mechanism.

14. The system of claim 13 wherein said data-processing apparatus and said module are further operable in combination with one another to increment said sequence number in response to instantiating said plurality of global data structures.

15. The system of claim 13 wherein said data-processing apparatus and said module are further operable in combination with one another to:

utilize said compiler directive mechanism to enable/disable a memory leak detection and an isolation algorithm on a work-as-needed basis;

utilize a smaller size variable for said sequence number;

define said plurality of sequence number zones based on debug needs; and

combine said optimization and said performance tuning operation with at least one other memory leak detection and isolation operation.

16. The system of claim 12 wherein said data-processing apparatus and said module are further operable in combination with one another to:

instantiate a plurality of global data structures by allocating memory in said data-processing system prior to using said sequence number for indicating said order of memory allocation in said data-processing system;

isolate said plurality of memory leak blocks utilizing shell commands, task information, caller information, sequence number information, memory allocation size and a pointer to a next allocation memory block; and

perform an optimization and a performance tuning operation with respect to said data-processing system utilizing a compiler directive mechanism.

17. The system of claim 16 wherein said data-processing apparatus and said module are further operable in combination with one another to

utilize said compiler directive mechanism to enable/disable a memory leak detection and an isolation algorithm on a work-as-needed basis;

utilize a smaller size variable for said sequence number;

define said plurality of sequence number zones based on debug needs; and

combine said optimization and said performance tuning operation with at least one other memory leak detection and isolation operation.

18. The system of clam 17 wherein said data-processing apparatus and said module are further operable in combination with one another to increment said sequence number in response to instantiating said plurality of global data structures.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE OF THE MERGER PREVIOUSLY RECORDED ON REEL 047642 FRAME 0417. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT, Recorded Mar 6, 2019
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To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
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MERGER Recorded Oct 5, 2018
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To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
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TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
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PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
CHANGE OF NAME Recorded Jun 6, 2014
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
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PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 7, 2007
From: YANG, JINCHAO
To: LSI LOGIC CORPORATION
Reel/Frame 019083/0623 →