Spread spectrum block control apparatus and spread spectrum clock generating apparatus
View Patent ↗A phase interpolator receives an input clock signal and varies the phase of an output clock signal in accordance with a phase control signal. An SSC controller, which generates the phase control signal applied to the phase interpolator, includes a pre-divider for outputting a frequency-divided clock obtained by frequency-dividing the input clock signal by a prescribed dividing value; a first counter receiving the frequency-divided clock from the frequency divider and repeatedly up-counting and down-counting by a predetermined first count, the first counter having a state machine for holding the present state; a second counter receiving the output signal of the first counter and repeatedly up-counting and down-counting by a predetermined second count, the second counter having a state machine for holding the present state; and a controller receiving the frequency-divided clock from the frequency divider, the counts from the first and second counters and the state of the second counter, and outputting a down signal, which retards the phase of the output clock signal, based upon the count values and states of the first and second counters at a timing decided by the frequency-divided clock. In the repetition of the counting operation of the first counter, the controller uses the same combinational logic. The controller has an inversion control circuit for inverting the signal when the states of the counters are predetermined prescribed states.
1. A spread spectrum clock control apparatus which exercises control to supply a phase control signal to a phase interpolator which receives an input clock signal and varies the phase of an output clock signal in accordance with the phase control signal, and to frequency-modulate the output clock signal, the apparatus comprising:
a first counter which receives a frequency-divided clock signal, changes over from up-counting to down-counting at a predetermined first count number, performs the up-counting and down-counting a prescribed number of times and outputs an output signal when a predetermined prescribed count number has been counted, said first counter having a state machine for managing transition of state;
a second counter which receives the output signal from said first counter and changes over from up-counting to down-counting at a predetermined second count number, said second counter having a state machine for managing transition of state; and
a controller which controls said phase control signal supplied to said phase interpolator, based upon count values of said first and second counters and state of said second counter.
2. The apparatus according to claim 1 , wherein the controller uses the same combinational logic as when the first counter repeats the counting operation.
3. The apparatus according to claim 1 , wherein said first counter makes state transitions sequentially from an initial state whenever there is a changeover between up-counting and down-counting, and, when a count equivalent to the prescribed count number makes one full cycle, returns the state to the initial state and outputs the output signal to thereby update the count value in said second counter.
4. The apparatus according to claim 1 , wherein said second counter changes over from up-counting to down-counting at the second count number, repeats a set of up-counting and down-counting operations a prescribed number of times, makes state transitions sequentially at every counting operation and returns the state to the initial state when the count makes one full cycle; and
said controller controls the number of times the phase control signal is activated in a predetermined reference period, based upon the count value in said first counter, the count value in said second counter and the state of said second counter.
5. The apparatus according to claim 4 , wherein said controller increases or decreases, in even-numbered units in response to one change in the count value in said second counter, thenumber of the phase control signals activated in the reference period.
6. The apparatus according to claim 4 , further comprising
a frequency dividing circuit which receives the input clock signal and frequency-divides the input clock signal to output the frequency-divided clock signal;
wherein said first counter counts the frequency-divided clock signal;
said controller receives the frequency-divided clock signal and the count values from said first and second counters; and
the reference period is stipulated by the product of a frequency division number in said frequency dividing circuit, the prescribed count number of said first counter and the clock period of the input clock signal.
7. The apparatus according to claim 4 , wherein said controller, in regard to deciding the number of active states of the phase control signal in the reference period, from the count value in said first counter, the count value in said second counter and the state thereof, includes a control circuit which, in a case where the state of said second counter is a predetermined one state, logically inverts a signal that was a non-inverting signal in another state of said second counter corresponding to the one state.
8. The apparatus according to claim 1 , wherein said controller outputs to said phase interpolator a down signal, which retards the phase of the output clock signal, as the phase control signal.
9. The apparatus according to claim 1 , wherein said controller outputs to said phase interpolator a down signal, which retards the phase of the output clock signal, or an up signal, which advances the phase of the output clock signal, as the phase control signal.
10. The apparatus according to claim 1 , wherein said controller outputs to said phase interpolator a down signal, which retards the phase of the output clock signal, and an up signal, which advances the phase of the output clock signal, as the phase control signal, and holds the up and down states.
11. The apparatus according to claim 10 , wherein the controller uses the same combinational logic as when the first counter repeats the counting operation in up-counting and down-counting operations.
12. A spread spectrum clock generating apparatus comprising
a phase interpolator which receives an input clock signal and varies the phase of an output clock signal in accordance with a phase control signal; and
a spread spectrum clock control apparatus which exercises control to supply the phase control signal to said phase interpolator and to frequency-modulate the output clock signal;
wherein said spread spectrum clock control apparatus is the spread spectrum clock control apparatus set forth in claim 1 .