Semiconductor device
View Patent ↗There is provided a semiconductor device including a first logic circuit to operate based on a first power supply and a second power supply, and a second logic circuit to operate based on the first power supply and a third power supply boosted from the second power supply. The second logic circuit includes a holding section to hold a value generated according to a first signal and a second signal operating asynchronously with respect to each other.
1. A semiconductor device, comprising:
a first power supply;
a second power supply;
a first logic circuit configured to operate based on the first power supply and the second power supply;
a third power supply; and
a second logic circuit configured to operate based on the first power supply and the third power supply,
wherein the third power supply is boosted from the second power supply, and
wherein the second logic circuit includes a holding section configured to hold a value generated according to a first signal and a second signal operating asynchronously with respect to each other.
2. The semiconductor device according to claim 1 , wherein
the second logic circuit is a latch circuit configured to hold a value generated according to the first signal and the second signal.
3. The semiconductor device according to claim 1 , wherein
the second logic circuit is configured to hold a first state for a period after a logic value of the first signal changes until a logic value of the second signal changes, and further configured to hold a second state for a period after a logic value of the second signal changes until a logic value of the first signal changes.
4. The semiconductor device according to claim 1 , wherein
the third power supply is generated inside the semiconductor device and supplies a voltage to a circuit other than the second logic circuit.
5. A semiconductor device, comprising:
a state holding circuit configured to operate according to a first signal and a second signal operating asynchronously with respect to the first signal, the state holding circuit including a holding section configured to hold a value generated according to the first signal and the second signal; and
a processor configured to operate according to the first signal and an output of the state holding circuit,
wherein the holding section comprises a transistor having a smaller resistance in a conducting state than a transistor of the processor, to receive an output of the state holding circuit, and
wherein the transistor used for the holding section receives a boosted voltage generated on the basis of a power supply supplied to the semiconductor device.
6. The semiconductor device according to claim 5 , wherein the transistor used for the holding section has a lower threshold voltage than the transistor of the processor to receive an output of the state holding circuit.
7. The semiconductor device according to claim 5 , wherein the transistor used for the holding section has a plurality of threshold voltages.
8. The semiconductor device according to claim 5 , wherein the transistor used for the holding section has a variable threshold voltage.
9. A semiconductor device, comprising:
a booster configured to operate based on a first power supply and a second power supply and to generate a third power supply boosted from the second power supply; and
a logic circuit configured to operate based on the first power supply and the third power supply,
wherein the logic circuit comprises a first circuit and a holding section,
wherein the first circuit is configured to operate according to a first signal and a second signal, the first signal and the second signal input asynchronously with respect to each other, and
wherein the holding section is configured to hold an output of the first circuit.
10. The semiconductor device according to claim 1 ,
wherein the third power supply is provided by a booster configured to step up the second power supply, and
wherein the booster operates according to a voltage of the second power supply and a voltage of the first power supply.
11. The semiconductor device according to claim 10 , wherein the booster is a charge pump.
12. The semiconductor device according to claim 5 , wherein the boosted voltage is provided by a booster inside the semiconductor device and configured to boost a voltage of the power supply.
13. The semiconductor device according to claim 12 , wherein the booster is a charge pump.
14. The semiconductor device according to claim 9 , wherein the booster is provided inside the semiconductor device.
15. The semiconductor device according to claim 9 , wherein the booster is a charge pump.