High speed multi-modulus prescalar divider
View Patent ↗A system and method are provided for multi-modulus division. The method accepts an input first signal having a first frequency and divides the first frequency by an integral number. A second signal is generated with a plurality of phase outputs, each having a second frequency. Using a daisy-chain register controller, phase outputs are selected and supplied as a third signal with a frequency. Selecting phase outputs using the daisy-chain register controller includes supplying the third signal as a clock signal to registers having outputs connected in a daisy-chain. Then, a sequence of register output pulses is generated in response to the clock signals, and register output pulses are chosen from the sequence to select second signal phase outputs. By using 8-second signal phase outputs, a third signal is obtained with a frequency equal to the second frequency multiplied by one of the following numbers: 0.75, 0.875, 1, 1.125, or 1.25.
1. A method for multi-modulus division, the method comprising:
accepting an input first signal having a first frequency;
dividing the first frequency by an integral number;
generating a second signal with a plurality of a first number of equally-spaced phase outputs, each having a second frequency;
using a daisy-chain register controller, selecting phase outputs as follows:
supplying a third signal as a clock signal to registers having outputs connected in a daisy-chain;
generating a sequence of register output pulses in response to the clock signal by selecting a first pattern of register output pulses generated exclusively from a single register; and,
using the generated sequence of register output pulses to select the second signal phase outputs; and,
supplying the selected phase outputs as the third signal as follows:
supplying phase output pulses having a non-varying first period; and,
generating the third signal having the second frequency.
2. The method of claim 1 wherein generating the sequence of register output pulses includes selecting a second pattern of register output pulses;
wherein supplying the selected phase outputs as the third signal includes:
supplying phase output pulses having a second period, different from the first period; and,
generating a third signal with a third frequency, different from the second frequency.
3. The method of claim 2 wherein supplying phase output pulses having a second period, different from the first period, includes supplying phase output pulses having a second period, greater than the first period; and,
wherein generating the third signal includes generating a third signal third frequency, lower than the second frequency.
4. The method of claim 3 wherein supplying phase output pulses having a second period, greater than the first period, includes:
selecting an initial phase output having an initial phase;
selecting a subsequent phase output having a phase greater than the initial phase; and,
wherein generating the third frequency includes generating the third frequency in response to advancing the phase between initial and subsequent phase outputs.
5. The method of claim 2 wherein supplying phase output pulses having a second period, different from the first period, includes supplying phase output pulses having a second period, smaller than the first period; and,
wherein generating the third signal includes generating a third signal third frequency, greater than the second frequency.
6. The method of claim 5 wherein supplying phase output pulses having a second period, smaller than the first period, includes:
selecting an initial phase output having an initial phase;
selecting a subsequent phase output having a phase less than the initial phase; and,
wherein generating the third frequency includes generating the third frequency in response to lagging the phase between initial and subsequent phase outputs.
7. The method of claim 2 generating a third signal with a third frequency, different from the second frequency, includes generating a third signal third frequency that is a non-integer quotient of the second frequency.
8. The method of claim 1 wherein generating the second signal with the first number of equally-spaced phase outputs includes generating eight second signal outputs, each output offset from an adjoining output by 45°; and,
wherein generating the third signal includes generating a third signal with a frequency equal to the second frequency multiplied by a number selected from a group consisting of 0.75, 0.875, 1, 1.125, and 1.25.
9. The method of claim 7 wherein generating the second signal includes generating a second signal with a frequency equal to the first frequency divided by four.
10. A system for multi-modulus division, the system comprising:
a divider module having an input to accept a first signal having a first frequency, the divider module dividing the first frequency by an integral number and supplying a second signal with a plurality of a first number of equally-spaced phase outputs, each having a second frequency;
a phase selection multiplexer having an input to accept the plurality of second signal phase outputs, and a second input to accept a control signal, and an output to supply a second signal phase selected in response to the control signal;
a daisy-chain register controller including a plurality of registers with daisy-chain-connected outputs, the daisy-chain register controller accepting a third signal as the register clock signal, generating a sequence of register output pulses in response to the clock signal by selecting a first pattern of register output pulses generated exclusively from a single register, and using the generated sequence of register output pulses as the control signal supplied at the second input to the phase selection multiplexer for selecting the second signal phase outputs; and,
wherein the phase selection multiplexer supplies the selected phase outputs as the third signal having a non-varying first period and the second frequency.
11. The system of claim 10 wherein the daisy-chain register controller selects a second pattern of register output pulses; and,
wherein the phase selection multiplexer supplies phase outputs having a second period, different from the first period, as a third signal with a third frequency, different from the second frequency.
12. The system of claim 11 wherein the phase selection multiplexer supplies phase outputs having a second period, greater than the first period, creating a third signal third frequency, lower than the second frequency.
13. The system of claim 11 wherein the phase selection multiplexer supplies phase outputs having a second period, less than the first period, creating a third signal third frequency, higher than the second frequency.
14. The system of claim 11 wherein the phase selection multiplexer supplies phase outputs having a second period, different from the first period, creating a third signal third frequency that is a non-integer quotient of the second frequency.
15. The system of claim 10 wherein the divider module supplies eight second signal outputs, each output offset from an adjoining output by 45°; and,
wherein the phase selection multiplexer creates a third signal with a frequency equal to the second frequency multiplied by a number selected from a group consisting of 0.75, 0.875, 1, 1.125, and 1.25.
16. The system of claim 15 wherein the divider module supplies a second signal with a second frequency equal to the first frequency divided by four.