IP Library › Assignment 042444/0891
Patent Assignment
Reel/Frame 042444/0891

Security Interest

Recorded: 2017-05-11 Received: 2017-05-11 Pages: 42
Assignor
Assignee
GOLDMAN SACHS BANK USA, AS COLLATERAL AGENT
200 WEST STREET, NEW YORK, NY, 10282, UNITED STATES
Covered Properties (100)
Techniques for Statistical Frequency Enhancement of Statically Timed Designs
Application: 15/414,739 →
Power Optimization Mechanisms for Framers by Using Serial Comparison in Frame Alignment Process
Application: 15/389,179 →
Power Optimization Mechanisms for Framers by Selectively Deactivating Frame Alignment Process
Application: 15/389,140 →
Power Optimization Mechanisms for Framers by Serializing Frame Alignment Processes for Multiple Lanes
Application: 15/389,165 →
Method to Dynamically Inject Errors in a Repairable Memory on Silicon and a Method to Validate Built-in-Self-Repair Logic
Application: 15/384,437 →
Write Assist for Memories with Resistive Bit Lines
Application: 15/372,581 →
Optimizing Memory Mapping(S) Associated with Network Nodes
Application: 15/366,251 →
Memory Page Request for Optimizing Memory Page Latency Associated with Network Nodes
Application: 15/351,477 →
Mitigating Interaction Between Adaptive Equalization and Timing Recovery
Application: 15/336,435 →
Clock Control Based on Voltage Associated with a Microprocessor
Application: 15/256,787 →
Managing a Data Packet for an Operating System Associated with a Multi-Node System
Application: 15/250,966 →
Resolving Interaction Between Channel Estimation and Timing Recovery
Application: 15/191,229 →
Retrieval Hash Index
Application: 15/157,597 →
Timing Recovery with Adaptive Channel Response Estimation
Application: 15/151,154 →
Efficient Techniques for Process Variation Reduction for Static Timing Analysis
Application: 15/149,249 →
Mimcap Creation and Utilization Methodology
Application: 15/149,244 →
High Speed Serializer Using Quadrature Clocks
Application: 15/137,187 →
Data Managment for Cache Memory
Application: 15/098,573 →
Dc Offset Calibration of Adc with Alternate Comparators
Application: 15/076,338 →
Self-Referenced on-Die Voltage Droop Detector
Application: 15/068,737 →
Multiple-Queue Integer Coalescing Mapping Algorithm with Shared Based Time
Application: 15/015,338 →
High Speed Add-Compare-Select for Viterbi Decoder
Application: 14/961,228 →
Package Programmable Decoupling Capacitor Array
Application: 14/838,778 →
Method And Apparatus For Medical Imaging Using Differencing Of Multiple Fluorophores
Application: 14/767,836 →
Systems and Methods Facilitating Reduced Latency via Stashing in System on Chips
Application: 14/796,167 →
Split Loop Timing Recovery
Application: 14/736,754 →
Calibration and Tracking of Receiver
Application: 14/736,874 →
High Efficiency Half-Cross-Coupled Decoupling Capacitor
Application: 14/736,882 →
Prefetch Tag for Eviction Promotion
Application: 14/710,837 →
Main Memory Prefetch Operation and Multiple Prefetch Operation
Application: 14/666,771 →
Clock Phase Adaptation for Precursor Isi Reduction
Application: 14/619,952 →
Generating and/or Employing a Descriptor Associated with a Memory Translation Table
Application: 14/566,945 →
Flexible and Robust Power Grid Connectivity
Application: 14/519,271 →
Generating a Pulse Clock Signal Based on a First Clock Signal and a Second Clock Signal
Application: 14/497,629 →
Priority Framework for a Computing Device
Application: 14/497,619 →
Frequency Synthesis with Gapper and Multi-Modulus Divider
Application: 14/469,456 →
High Speed Transceiver Based on Concatenates of a Leech Lattice with Binary and Nonbinary Codes
Application: 14/466,347 →
High Speed Transceiver Based on Embedded Leech Lattice Constellation
Application: 14/466,334 →
Product Coded Modulation Scheme Based on E8 Lattice and Binary and Nonbinary Codes
Application: 14/466,372 →
Data Dependent Jitter Reduction of Switch Driver Signals in High Speed Current Steering Digital-to-Analog Converters
Application: 14/466,316 →
Concatenates of an E8 Lattice with Binary and Non Binary Codes
Application: 14/466,361 →
Systems and Methods Facilitating Multi-Word Atomic Operation Support for System on Chip Environments
Application: 14/264,716 →
Implementation of Load Acquire/Store Release Instructions Using Load/Store Operation with Dmb Operation
Application: 14/243,949 →
Identification Codewords for a Rate-Adapted Version of a Data Stream
Application: 14/222,913 →
High Frequency Voltage Supply Monitor
Application: 14/208,408 →
Hazard Prediction for a Group of Memory Access Instructions Using a Buffer Associated with Branch Prediction
Application: 14/203,896 →
Generating a Timeout Signal Based on a Clock Counter Associated with a Data Request
Application: 14/191,923 →
Method for Manufacturing a Photodetector Having a Bandwidth Tuned Honeycomb Cell Photodiode Structure
Application: 14/171,339 →
Calibration of High-Speed Interleaved Arrays
Application: 14/162,899 →
Programmable Gain Amplifier with Controlled Gain Steps
Application: 14/162,896 →
Flow Pinning in a Server on a Chip
Application: 14/162,903 →
Allocation of Load Instruction(S) to a Queue Buffer in a Processor System Based on Prediction of an Instruction Pipeline Hazard
Application: 14/100,228 →
Jitter Mitigating Phase Locked Loop Circuit
Application: 14/061,307 →
Defect Propagation of Multiple Signals of Various Rates When Mapped into a Combined Signal
Application: 14/053,032 →
Mapping a Plurality of Signals to Generate a Combined Signal Comprising a Higher Data Rate Than a Data Rate Associated with the Plurality of Signals
Application: 14/027,518 →
Reformating a Plurality of Signals to Generate a Combined Signal Comprising a Higher Data Rate Than a Data Rate Associated with the Plurality of Signals
Application: 14/021,035 →
System and Method for Process, Voltage, Temperature (Pvt) Stable Differential Amplifier Transfer Function
Application: 14/021,834 →
Discrete Time Compensation Mechanisms
Application: 14/016,534 →
Transmision Over Reduced Pairs of Twinex Cables and Communication Coding
Application: 61/869,395 →
Address Index Recovery Using Hash-Based Exclusive Or
Application: 13/967,607 →
Fast Filtering for a Transceiver
Application: 13/965,375 →
End-To-End Flow Control in System on Chip Interconnects
Application: 13/953,059 →
Adaptive Spectral Enhancement and Harmonic Separation
Application: 13/910,779 →
Method and Apparatus for Smoothing Jitter Generated by Byte Stuffing
Application: 13/865,843 →
Integrated Circuit Memory Device with Read-Disturb Control
Application: 13/863,208 →
Detection and Estimation of Narrowband Interference by Matrix Multiplication
Application: 13/854,675 →
Cache Miss Detection Filter
Application: 13/848,828 →
Dynamic Power Control
Application: 13/848,377 →
Method and Apparatus for Gapping
Application: 13/846,171 →
Frequency Synthesis with Gapper
Application: 13/846,311 →
Virtual Appliance on a Chip
Application: 13/838,624 →
Processor Hang Detection and Recovery
Application: 13/838,440 →
Debugging Processor Hang Situations Using an External Pin
Application: 13/803,906 →
Broadcast Messaging and Acknowledgment Messaging for Power Management in a Multiprocessor System
Application: 13/799,268 →
System Boot with External Media
Application: 13/772,498 →
Large Receive Offload Functionality for a System on Chip
Application: 13/772,535 →
Systems and Methods for Queue Request Ordering Without Stalling Requests in Aliasing Conditions by Using a Hash Indexed Based Table
Application: 13/752,161 →
Fractional Phase-Locked Loop with Dynamic Divide Ratio Adjustment
Application: 13/747,053 →
System and Method for Sata Virtualization and Domain Protection
Application: 13/742,767 →
Programmable Resistance-Modulated Write Assist for a Memory Device
Application: 13/726,800 →
Imaging System for Passive Alignment of Engines
Application: 13/661,490 →
Expanded Beam Interconnector
Application: 13/654,493 →
Self-Test Design for Serializer / Deserializer Testing
Application: 13/654,833 →
High-Density Fiber Coupling and Emission/Detection System
Application: 13/645,629 →
Collimated Beam Channel with Four Lens Optical Surfaces
Application: 13/645,627 →
Managing Requests to Open and Closed Banks in a Memory System
Application: 13/644,924 →
Imaging System for Passive Alignment of Engines
Application: 61/707,434 →
Expanded Beam Interconnector
Application: 61/706,653 →
Device and Method for a Multiplexor/Demultiplexor Reset Scheme
Application: 13/607,136 →
System and Method for Scaling Total Client Capacity with a Standard-Compliant Optical Transport Network (OTN)
Application: 13/536,841 →
Chromatic Dispersion Pre-Compensation
Application: 13/461,847 →
Ultra Low-Noise True Sub-Volt Band Gap
Application: 13/454,973 →
Network Synchronized Time Base Timer
Application: 13/444,382 →
Linear Source Follower Amplifier
Application: 13/437,154 →
Clock Generation for N.5 Modulus Divider
Application: 13/427,955 →
Method and Apparatus for Performing Table Lookup
Application: 13/422,979 →
Latch Isolation Circuit
Application: 13/422,755 →
Optimized Chromatic Dispersion Filter
Application: 13/413,705 →
Pseudo Single-Phase Flip-Flop (Psp-Ff)
Application: 13/412,679 →
System and Method for Pre-Fetching Data Based on a Fifo Queue of Packet Messages Reaching a First Capacity Threshold
Application: 13/398,679 →