Power optimization mechanisms for framers by using serial comparison in frame alignment process
System and method of frame alignment at a receiver with power optimization mechanisms. A framer uses one or more comparators to search for the FAW in the incoming data, with each comparator configured to serially compare multiple windows of a parallel M-bit block (as provided from a parallel data bus) with the FAW. Multiple comparators in the framer may operate in parallel to search for the FAW at different windows. This configuration can significantly reduce the comparator count and so the gate count as well as the chip area in a framer. Power consumption can be advantageously reduced as one comparator operating serially consumes less power than multiple comparators in parallel because less gate toggling is involved.
1. A receiver in a telecommunication system, the receiver comprising:
an input interface configured to receive a data stream comprising a plurality of frames, wherein a respective frame of said plurality of frames comprises a frame alignment word;
a serial-to-parallel converter coupled to said input interface and configured to output a block of R bits from said data stream in parallel; and
frame alignment logic coupled to said serial-to-parallel converter, wherein said frame alignment logic comprises a comparator of W bits configured to serially compare a plurality of W-bit windows with said frame alignment word to locate said frame alignment word in said data stream, wherein said serial-to-parallel converter is configured to maintains said block of R bits during said comparator serially comparing said plurality of W-bit windows with said frame alignment word, wherein each of said plurality of W-bit windows is extracted from said block of R bits and has a respective location in said block of R bits, and wherein R and W are integers greater than 0 and W<R.
2. The receiver of claim 1 , wherein said frame alignment logic comprises a plurality of comparators of W bits, wherein a respective comparator of said plurality of comparators is configured to serially compare multiple W-bit windows of said plurality of W-bit windows with said frame alignment word, and wherein said plurality of comparators operate in parallel.
3. The receiver of claim 2 , wherein said respective comparator is configured to compare said multiple W-bit windows with said frame alignment word in successive periods of time.
4. The receiver of claim 1 , wherein said frame alignment word comprises W bits, and wherein said plurality of frames are of a same length.
5. The receiver of claim 1 , wherein said serial-to-parallel converter is coupled to said frame alignment logic through an R-bit parallel data bus.
6. The receiver of claim 1 , wherein said frame alignment logic is configured to enter a power conservation state responsive to said frame alignment word being located in said data stream.
7. A receiver in a telecommunication system, said receiver comprising:
an input interface configured to receive a data stream comprising a plurality of frames, wherein a respective frame of said plurality of frames comprises a frame alignment word;
a data bus coupled to said input interface and configured to output a block of R bits from said data stream in parallel; and
a comparator coupled to said data bus configured to successively compare a plurality of W-bit windows with said frame alignment word to locate said frame alignment word in said data stream, wherein said plurality of W-bit windows have respective bit locations within said block of R bits, and wherein R and W are integers, wherein said comparator is configured to compare said plurality of W-bit windows with said frame alignment word in successive clock cycles, and wherein said data bus is coupled to a serial-to-parallel converter configured to maintain said block of R bits during said successive clock cycles.
8. The receiver of claim 7 comprising a framer coupled to said data bus and comprising a plurality of comparators, said plurality of comparators comprising said comparator, wherein each comparator in said framer is configured to successively compare a respective plurality of W-bit windows with said frame alignment word.
9. The receiver of claim 8 , wherein said framer is configured to enter a power reduction state based on an event that said frame alignment word being located in said data stream.
10. The receiver of claim 9 further comprising error detection logic coupled to said framer, wherein said framer is further configured to exit said power reduction state responsive to said error detection logic detecting an error that is greater than a prescribed limit.
11. The receiver of claim 8 , wherein said framer is configured to cause said plurality of comparators to stop comparing said block of R-bits with said frame alignment word responsive to said frame alignment word being located in said data stream.
12. The receiver of claim 8 , wherein said plurality of comparators are configured to operate in parallel.
13. The receiver of claim 7 , wherein said frame alignment word comprises W bits, and wherein said plurality of frames have a same length.
14. A method of frame alignment at a receiver in a telecommunication system, said method comprising:
receiving a data stream comprising a plurality of frames, wherein a respective frame of said plurality of frames comprises a frame alignment word;
converting a sequence of R bits from said data stream to a parallel W-bit block; and
successively comparing a plurality of W-bit windows with said frame alignment word by a comparator to locate said frame alignment word in said data stream, wherein said plurality of W-bit windows have respective bit locations within said parallel R-bit block, and wherein R and W are integers.
15. The method of claim 14 further comprising comparing multiple W-bit windows with said frame alignment word in parallel by multiple comparators, wherein said multiple W-bit windows have respective bit locations within said parallel R-bit block.
16. The method of claim 15 further comprising disabling said successively comparing
based on an event that said frame alignment word being located in said data stream.
17. The method of claim 16 further comprising exiting said power reduction state responsive to a detected error being greater than a prescribed limit, wherein said detected error is detected through a forward error correction process.
18. The method of claim 14 further comprising stopping comparing said plurality of W-bit windows with said frame alignment word responsive to said frame alignment word being located in said data stream.