System and method for pre-fetching data based on a FIFO queue of packet messages reaching a first capacity threshold

1. In a system-on-chip (SoC) with a processor, a method for pre-fetching packet data prior to processing, the method comprising:

accepting a plurality of packets;

writing each packet into a memory;

deriving a message for each packet, where each message includes a packet descriptor with a pointer to an address of the packet in the memory;

adding each message to a tail of a first-in first-out (FIFO) queue;

a pre-fetch module examining a first message if the first message reaches a first capacity threshold of the FIFO queue;

if the first message reaches the first capacity threshold, the pre-fetch module reading a first packet associated with the first message, from the memory;

loading the first packet into cache memory;

a processor reading the first message from a head of the FIFO queue; and,

in response to reading the first message, the processor reading the previously loaded first packet from cache memory.

2. The method of claim 1 wherein writing each packet into the memory includes writing an associated state of each packet into memory, where the associated state includes information selected from a group consisting of a packet destination address, a packet source address, an egress port number, status of on-going communications, and combinations of the above-listed information;

wherein deriving the message for each packet includes adding a pointer to the message for each packet directed to an address in memory for a corresponding associated state;

wherein the pre-fetch module reading the first packet from memory includes the pre-fetch module additionally reading a first associated state, corresponding to the first packet, from memory;

wherein loading the first packet into cache memory includes additionally loading the first associated state into cache memory; and,

wherein reading the first packet from cache memory includes the processor additionally reading the first associated state from cache memory.

3. The method of claim 1 wherein adding each message to the tail of the FIFO queue includes:

differentiating the messages into a first plurality of categories on the basis of a system policy;

adding messages into the tail of a virtual FIFO queue having a corresponding first plurality of parallel physical queues; and,

wherein the pre-fetch module examining the first message at the head of the FIFO queue includes the pre-fetch module selectively examining messages reaching the first capacity threshold of each parallel physical queue in response to the system policy.

4. The method of claim 3 wherein differentiating the messages into the first plurality of categories on the basis of the system policy includes differentiating messages on the basis of a ranked priority of categories, where the ranked priority of categories is associated with a ranked priority of parallel physical queues; and,

wherein the pre-fetch module selectively examining messages reaching the first capacity threshold of each parallel physical queue includes the pre-fetch module examining messages in a higher priority queue prior to examining messages in a lower priority queue.

5. The method of claim 1 further comprising:

measuring if the first message reaches a second capacity threshold in the FIFO queue; and,

if the first message does not reach the second capacity threshold, automatically stashing the first packet in cache memory, without the pre-fetch module examining the first message.

6. The method of claim 1 wherein the pre-fetch module examining the first message, if the first message reaches the first capacity threshold of the FIFO queue, includes there being a relationship between the first capacity threshold of the FIFO second and a cache memory capacity.

7. In a system-on-chip (SoC) with a processor, a system for pre-fetching packet data prior to processing, the system comprising:

a cache memory;

an Ethernet media access control (MAC) receiver having a network interface to accept a plurality of packets, an interface to write each packet into a memory, and an interface to supply a descriptor for each packet;

a messenger module state machine having an interface to accept the descriptor for each packet and having an output to supply a message for each packet, where each message includes the packet descriptor with a pointer to an address of the packet in memory;

a first-in first-out (FIFO) queue having a tail to accept each message, a head to supply each message, and a first capacity threshold tap;

a pre-fetch module state machine having an input to connected to the first capacity threshold tap to examine a first message, if the first message reaches the first capacity threshold tap of the FIFO queue, the pre-fetch module state machine having an output to supply commands for reading a first packet associated with the first message from the memory, and loading the first packet into the cache memory; and,

a processor having an interface for reading the first message from the head of the FIFO queue, and in response to reading the first message, reading the previously loaded first packet from the cache memory.

8. The system of claim 7 wherein the Ethernet MAC receiver writes an associated state of each packet into memory, where the associated state includes information selected from a group consisting of a packet destination address, a packet source address, an egress port number, status of on-going communications, and combinations of the above-listed information;

wherein the messenger module state machine adds a pointer to the message for each packet directed to an address in memory for a corresponding associated state;

wherein the pre-fetch module additionally reads a first associated state, corresponding to the first packet, from memory, in response to examining the first message, and loads the first associated state into the cache memory; and,

wherein the processor additionally reads the first associated state from cache memory.

9. The system of claim 7 wherein the FIFO queue is a virtual FIFO queue having a first plurality of parallel physical queues;

wherein the messenger module state machine differentiates the messages into a first plurality of categories on the basis of a system policy, and adds the messages to the tail of a corresponding physical queue; and,

the system further comprising:

an arbitrator state machine having an input connected to the first capacity threshold tap of each physical queue and an output connected to the pre-fetch module input, the arbitrator state machine selectively supplying the pre-fetch module with a status of messages reaching the first capacity threshold of each parallel physical queue in response to the system policy.

10. The system of claim 9 wherein the messenger module state machine differentiates messages on the basis of a ranked priority of categories, where the ranked priority of categories is associated with a ranked priority of parallel physical queues; and,

wherein the arbitrator state machine supplies message status to the pre-fetch module from a higher priority queue prior to supplying message status from a lower priority queue.

11. The system of claim 7 wherein the FIFO queue has a second capacity threshold tap;

wherein the pre-fetch module state machine has an input connected to the second capacity threshold tap for measuring if the first message reaches the second threshold capacity tap, and if the first messages does not reach the second threshold capacity tap, the pre-fetch module state machine sending commands for automatically stashing the first packet in cache memory, without examining the first message.

12. The system of claim 7 wherein the FIFO queue first capacity threshold is related to a cache memory capacity.