Patent Assignment
Reel/Frame 044798/0599
Assignment of Assignor's Interest
Recorded: 2017-11-21
Pages: 16
Assignor
MACOM CONNECTIVITY SOLUTIONS, LLC
Executed: 2017-10-25
Assignee
PROJECT DENVER INTERMEDIATE HOLDINGS LLC
4555 GREAT AMERICA PKWY #601, SANTA CLARA, CALIFORNIA, 95054
Covered Properties
(87)
Implementation of Load Acquire/Store Release Instructions Using Load/Store Operation with Dmb Operation
PCT:
PCT/US2015/041322 ↗
Flow Pinning in a Server on a Chip
PCT:
PCT/US2015/041911 ↗
High Frequency Voltage Supply Monitor
PCT:
PCT/US2015/042593 ↗
Systems and Methods Facilitating Multi-Word Atomic Operation Support for System on Chip Environments
PCT:
PCT/US2015/042595 ↗
Main Memory Prefetch Operation and Multiple Prefetch Operations
PCT:
PCT/US2015/042596 ↗
Priority Framework for a Computing Device
PCT:
PCT/US2015/042598 ↗
Generating and/or Employing a Descriptor Associated with a Memory Translation Table
PCT:
PCT/US2015/042600 ↗
Systems and Methods Facilitating Reduced Latency via Stashing in Systems on Chips
PCT:
PCT/US2015/042791 ↗
Prefetch Tag for Eviction Promotion
PCT:
PCT/US2015/042792 ↗
High Efficiency Half-Cross-Coupled Decoupling Capacitor
PCT:
PCT/US2015/042798 ↗
Package Programmable Decoupling Capacitor Array
PCT:
PCT/US2016/048857 ↗
Self-Referenced on-Die Voltage Droop Detector
PCT:
PCT/US2017/022022 ↗
Clock Control Based on Voltage Associated with a Microprocessor
PCT:
PCT/US2017/045825 ↗
Operating System with Hardware-Enabled Task Manager for Offloading Cpu Task Scheduling
Patent:
8,881,161 →
Application:
12/695,953 →
Multi-Processor System-On-Chip with Dynamic Packet Processing Load Control
Application:
12/756,128 →
Frequency Optimization Using Useful Skew Timing
Patent:
8,539,413 →
Application:
12/767,894 →
Packet Processing with Dynamic Load Balancing
Patent:
9,158,713 →
Application:
12/772,832 →
System and Method for Attached Storage Stacking
Patent:
8,499,012 →
Application:
12/818,870 →
Network-Attached Storage (Nas) Bandwidth Manager
Patent:
8,793,334 →
Application:
12/839,225 →
System and Method for Integrated Circuit Die Size Reduction
Patent:
8,762,915 →
Application:
12/884,264 →
System and Method for Packet Splitting
Patent:
8,732,351 →
Application:
12/917,425 →
Method and System for Queuing a Request by a Processor to Access a Shared Resource and Granting Access in Accordance with an Embedded Lock Id
Patent:
8,918,791 →
Application:
13/045,453 →
Shadow Latch
Patent:
8,618,856 →
Application:
13/077,949 →
Digital CMOS Circuit with Noise Cancellation
Patent:
8,384,421 →
Application:
13/092,084 →
Threshold Controlled Limited Out of Order Load Execution
Patent:
8,949,581 →
Application:
13/103,833 →
Integrated Circuit Module Time Delay Budgeting
Patent:
8,397,197 →
Application:
13/115,858 →
Pass Gate Shadow Latch
Patent:
8,497,721 →
Application:
13/160,569 →
Stashing System and Method for the Prevention of Cache Thrashing
Patent:
8,429,315 →
Application:
13/167,783 →
System and Method for Partitioning Resources in a System-on-Chip (SoC)
Patent:
8,893,267 →
Application:
13/212,112 →
Hazard-Free Minimal-Latency Flip-Flop (Hfml-Ff)
Patent:
8,421,514 →
Application:
13/225,044 →
Load Store Unit With Load Miss Result Buffer
Patent:
8,806,135 →
Application:
13/250,481 →
Outstanding Load Miss Buffer with Shared Entries
Patent:
8,850,121 →
Application:
13/250,544 →
Load Miss Result Buffer With Shared Data Lines
Patent:
8,793,435 →
Application:
13/250,596 →
System and Method for Updating a Data Structure
Patent:
8,762,362 →
Application:
13/278,701 →
System and Method for Controlling Updates of a Data Structure
Patent:
8,898,204 →
Application:
13/278,753 →
System and Method for Searching a Data Structure
Patent:
9,152,661 →
Application:
13/278,785 →
Packet Forwarding System and Method Using Patricia Trie Configured Hardware
Patent:
8,767,757 →
Application:
13/396,711 →
System and Method for Pre-Fetching Data Based on a Fifo Queue of Packet Messages Reaching a First Capacity Threshold
Patent:
9,336,162 →
Application:
13/398,679 →
Pseudo Single-Phase Flip-Flop (Psp-Ff)
Patent:
8,604,854 →
Application:
13/412,679 →
Method and Apparatus for Performing Table Lookup
Patent:
9,058,284 →
Application:
13/422,979 →
Multi-Level Store Merging in a Cache and Memory Hierarchy
Patent:
9,280,479 →
Application:
13/478,100 →
Managing Requests to Open and Closed Banks in a Memory System
Scheduling Memory Banks Based on Memory Access Patterns
Programmable Resistance-Modulated Write Assist for a Memory Device
Systems and Methods for Queue Request Ordering Without Stalling Requests in Aliasing Conditions by Using a Hash Indexed Based Table
Large Receive Offload Functionality for a System on Chip
Broadcast Messaging and Acknowledgment Messaging for Power Management in a Multiprocessor System
Virtual Appliance on a Chip
Dynamic Power Control
Cache Miss Detection Filter
Integrated Circuit Memory Device with Read-Disturb Control
End-To-End Flow Control in System on Chip Interconnects
Address Index Recovery Using Hash-Based Exclusive Or
Multi-Stage Address Translation for a Computing Device
Application:
14/042,957 →
Tcp Segmentation Offload in a Server on a Chip
Allocation of Load Instruction(S) to a Queue Buffer in a Processor System Based on Prediction of an Instruction Pipeline Hazard
Multi-Stage Address Translation for a Computing Device
Flow Pinning in a Server on a Chip
Hazard Prediction for a Group of Memory Access Instructions Using a Buffer Associated with Branch Prediction
High Frequency Voltage Supply Monitor
Implementation of Load Acquire/Store Release Instructions Using Load/Store Operation with Dmb Operation
Application:
14/243,949 →
Publication:
US 2015/0317158
Systems and Methods Facilitating Multi-Word Atomic Operation Support for System on Chip Environments
Pulse-Latch Based Bus Design for Increased Bandwidth
Priority Framework for a Computing Device
Flexible and Robust Power Grid Connectivity
Patent:
9,761,521 →
Application:
14/519,271 →
Generating and/or Employing a Descriptor Associated with a Memory Translation Table
Main Memory Prefetch Operation and Multiple Prefetch Operation
Prefetch Tag for Eviction Promotion
High Efficiency Half-Cross-Coupled Decoupling Capacitor
Patent:
9,438,225 →
Application:
14/736,882 →
Systems and Methods Facilitating Reduced Latency via Stashing in System on Chips
Package Programmable Decoupling Capacitor Array
Multiple-Queue Integer Coalescing Mapping Algorithm with Shared Based Time
Patent:
9,965,419 →
Application:
15/015,338 →
Self-Referenced on-Die Voltage Droop Detector
Data Managment for Cache Memory
Patent:
9,798,672 →
Application:
15/098,573 →
Mimcap Creation and Utilization Methodology
Patent:
9,876,007 →
Application:
15/149,244 →
Efficient Techniques for Process Variation Reduction for Static Timing Analysis
Patent:
10,318,696 →
Application:
15/149,249 →
Retrieval Hash Index
Managing a Data Packet for an Operating System Associated with a Multi-Node System
Patent:
10,819,783 →
Application:
15/250,966 →
Clock Control Based on Voltage Associated with a Microprocessor
Patent:
10,348,281 →
Application:
15/256,787 →
Memory Page Request for Optimizing Memory Page Latency Associated with Network Nodes
Patent:
10,439,960 →
Application:
15/351,477 →
Optimizing Memory Mapping(S) Associated with Network Nodes
Write Assist for Memories with Resistive Bit Lines
Method to Dynamically Inject Errors in a Repairable Memory on Silicon and a Method to Validate Built-in-Self-Repair Logic
Techniques for Statistical Frequency Enhancement of Statically Timed Designs
Variation Immune on-Die Voltage Droop Detector
Patent:
10,162,373 →
Application:
15/444,478 →
Data Managment for Cache Memory
Patent:
10,372,615 →
Application:
15/712,519 →
Pulse-Latch Based Bus Design for Increased Bandwidth
Application:
62/012,173 →
Related Assignments
(9)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Oct 7, 2013
From: ASHCRAFT, MATTHEW W.; FAVOR, JOHN GREGORY; KRUCKEMYER, DAVID A.
To: APPLIED MICRO CIRCUITS CORPORATION
Reel/Frame 031356/0374 →
Assignment of Assignor's Interest
Nov 8, 2013
From: ASHCRAFT, MATTHEW W.; FAVOR, JOHN GREGORY; KRUCKEMYER, DAVID A.
To: APPLIED MICRO CIRCUITS CORPORATION
Reel/Frame 031570/0586 →
Merger and Change of Name
Apr 6, 2017
From: APPLIED MICRO CIRCUITS CORPORATION; MACOM CONNECTIVITY SOLUTIONS, LLC; MACOM CONNECTIVITY SOLUTIONS, LLC
To: MACOM CONNECTIVITY SOLUTIONS, LLC
Reel/Frame 042176/0185 →
Merger and Change of Name
Apr 6, 2017
From: APPLIED MIRCO CIRCUITS CORPORATION; MACOM CONNECTIVITY SOLUTIONS, LLC
To: MACOM CONNECTIVITY SOLUTIONS, LLC
Reel/Frame 041889/0628 →
Merger and Change of Name
Apr 6, 2017
From: APPLIED MICRO CIRCUITS CORPORATION; MACOM CONNECTIVITY SOLUTIONS, LLC
To: MACOM CONNECTIVITY SOLUTIONS, LLC
Reel/Frame 041890/0429 →
Merger and Change of Name
Apr 7, 2017
From: APPLIED MICRO CIRCUITS CORPORATION; MACOM CONNECTIVITY SOLUTIONS, LLC
To: MACOM CONNECTIVITY SOLUTIONS, LLC
Reel/Frame 041933/0084 →
Security Interest
May 11, 2017
From: MACOM CONNECTIVITY SOLUTIONS, LLC (SUCCESSOR TO APPLIED MICRO CIRCUITS CORPORATION)
To: GOLDMAN SACHS BANK USA, AS COLLATERAL AGENT
Reel/Frame 042444/0891 →
Release of Security Interest
Oct 31, 2017
From: GOLDMAN SACHS BANK USA, AS COLLATERAL AGENT
To: MACOM CONNECTIVITY SOLUTIONS, LLC (SUCCESSOR TO APPLIED MICRO CIRCUITS CORPORATION)
Reel/Frame 044652/0609 →
Change of Name
Dec 6, 2017
From: PROJECT DENVER INTERMEDIATE HOLDINGS LLC
To: AMPERE COMPUTING LLC
Reel/Frame 044717/0683 →