A latch device is provided with a driver and a shadow latch. The driver has an input to accept a binary driver input signal, an input to accept a clock signal, and an input to accept a shadow-Q signal. The driver has an output to supply a binary Q signal equal to the inverse of the driver input signal, in response to the driver input signal, the shadow-Q signal, and the clock signal. The shadow latch has an input to accept the driver input signal, and an input to accept the clock signal. The shadow latch has an output to supply the shadow-Q signal equal to the inverted Q signal, in response to the driver input signal and clock signal.
1. A latch device comprising:
a driver comprising
an input to accept a binary driver input signal,
an input to accept a clock signal,
an input to accept a shadow-Q signal, and
an output to supply a binary Q signal equal to an inverse of the driver input signal, in response to the driver input signal, the shadow-Q signal, and the clock signal,
a first clocked inverter circuit having an input to accept the driver input signal, an input to accept the clock signal, and an output to supply the Q signal, and
a second clocked inverter circuit having an input to accept the shadow-Q signal, an input to accept the clock signal, and an output to supply the Q signal; and
a shadow latch having an input to accept the driver input signal, an input to accept the clock signal, and an output to supply the shadow-Q signal equal to an inverted Q signal, in response to the driver input signal and clock signal.
2. The circuit device of claim 1 wherein the shadow latch comprises:
a third clocked inverter circuit having an input to accept the driver input signal, an input to accept the clock signal, and an output to supply a D 1 signal;
a first inverter having an input to accept the D 1 signal and an output to supply the shadow-Q signal; and,
a fourth clocked inverter circuit having an input to accept the shadow-Q signal, an input to accept the clock signal, and an output to supply the D 1 signal.
3. The circuit device of claim 2 wherein the first clocked inverter comprises:
a first PMOS field effect transistor (FET) having a first source/drain (S/D) connected to a first do reference voltage, a second S/D, and a gate connected to receive the driver input signal;
a second PMOS FET having a first S/D connected to the second S/D of the first PMOS FET, a second S/D to supply the Q signal, and a gate to receive an inverted clock signal;
a first NMOS FET having a first S/D connected to the second S/D of the second PMOS FET, a second S/D, and a gate to receive the clock signal; and,
a second NMOS FET having a first S/D connected to the second S/D of the first NMOS FET, a second S/D connected to a second dc reference voltage having a lower potential than the first do reference voltage, and a gate to accept the driver input signal;
wherein the second clocked inverter comprises:
a third PMOS FET having a first S/D connected to the first dc reference voltage, a second S/D, and a gate connected to receive the shadow-Q signal;
a fourth PMOS FET having a first S/D connected to the second S/D of the third PMOS FET, a second S/D to supply the Q signal, and a gate to receive the clock signal;
a third NMOS FET having a first S/D connected to the second S/D of the fourth PMOS FET, a second S/D, and a gate to receive the inverted clock signal; and,
a fourth NMOS FET having a first S/D connected to the second S/D of the third NMOS FET, a second S/D connected to the second do reference voltage, and a gate to accept the shadow-Q signal.
4. The circuit device of claim 3 wherein the third clocked inverter comprises:
a fifth PMOS FET having a first S/D connected to the first dc reference voltage, a second S/D, and a gate connected to receive the driver input signal;
a sixth PMOS FET having a first S/D connected to the second S/D of the fifth PMOS FET, a second S/D to supply the D 1 signal, and a gate to receive the inverted clock signal;
a fifth NMOS FET having a first S/D connected to the second S/D of the sixth PMOS FET, a second S/D, and a gate to receive the clock signal; and,
a sixth NMOS FET having a first S/D connected to the second S/D of the fifth NMOS FET, a second S/D connected to the second dc reference voltage, and a gate to accept the driver input signal;
wherein the fourth clocked inverter comprises:
a seventh PMOS FET having a first S/D connected to the first dc reference voltage, a second S/D, and a gate connected to receive the shadow-Q signal;
an eighth PMOS FET having a first S/D connected to the second S/D of the seventh PMOS FET, a second S/D to supply the D 1 signal, and a gate to receive the clock signal;
a seventh NMOS FET having a first S/D connected to the second S/D of the eighth PMOS FET, a second S/D, and a gate to receive the inverted clock signal; and,
an eighth NMOS FET having a first S/D connected to the second S/D of the seventh NMOS FET, a second S/D connected to the second dc reference voltage, and a gate to accept the shadow-Q signal.
5. The circuit device of claim 2 wherein the third clocked inverter supplies the D 1 signal during the first polarity of the clock signal; and,
wherein the fourth clocked inverter supplies the D 1 signal during the second polarity of the clock signal.
6. The circuit device of claim 1 wherein the first clocked inverter supplies the Q signal during a first polarity of the clock signal; and,
wherein the second clocked inverter supplies the Q signal during a second polarity of the clock signal.
7. A method for stabilizing an unbuffered latch, comprising:
providing a single gate delay driver;
supplying a binary driver input signal, with a first polarity, to an input of the driver;
in response to a first clock signal, transferring a second polarity of the driver input signal to a driver (Q) output, with no more than one gate delay;
regardless of spurious signals received at the driver output, maintaining the second polarity at the driver (Q) output until a second clock signal is received, subsequent to the first clock signal, wherein maintaining the second polarity of the driver (Q) output comprises maintaining the second polarity in response to the shadow-Q signal; and
generating a shadow-Q signal in response to the first clock signal, wherein generating the shadow-Q signal comprises generating the shadow-Q signal decoupled from the driver (Q) output.
8. The method of claim 7 wherein providing the driver and shadow latch comprises providing the driver with a clocked transfer inverter output (Q) connected to a clocked hold inverter output and providing the shadow latch with a clocked transfer inverter driving a clocked hold inverter's feedback input; and,
wherein maintaining the second polarity of the driver (Q) output comprises supplying the shadow-Q signal to an input of the driver clocked hold inverter.
9. A single gate delay latch comprising:
a first circuit having an interface to accept an input signal with a first binary state, an interface to accept a binary clock signal, and an interface to supply a Q signal with a second binary state opposite to the first binary state and delayed by a single gate, the first circuit maintaining the Q signal second binary state during a first clock polarity;
a second circuit having an interface to accept a shadow-Q signal, and interface to accept the clock signal, and an interface to supply the Q signal, the second circuit maintaining the Q signal second binary state during a second clock polarity, opposite to the first polarity, wherein the second circuit is a clocked inverter; and,
a shadow circuit having an interface to accept the input signal with the first binary state, an interface to accept the clock signal and an interface to supply the shadow-Q signal.
10. A master-slave flip-flop comprising:
the single gate delay master latch of claim 9 series-connected to a single gate delay slave-driver, the master latch having a D input to accept a binary first signal with a first polarity; and,
regardless of spurious signals received at the slave latch output, a means for maintaining the first signal first polarity at the slave-driver output until a subsequent clock signal is received.
11. The latch of claim 9 wherein the first circuit is a clocked inverter; and,
wherein the second circuit is a clocked inverter.
12. The latch of claim 9 wherein the shadow circuit comprises:
a third circuit having an interface to accept the input signal with the first binary state, an interface to accept the clock signal, and an interface to supply a D 1 signal with the second binary state, delayed by a single gate, the third circuit maintaining the D 1 signal second binary state during the first clock polarity;
an inverter having an input to accept the D 1 signal and an output to supply the shadow-Q signal; and,
a fourth circuit having an interface to accept the shadow-Q signal, and interface to accept the clock signal, and an interface to supply the D 1 signal, the fourth circuit maintaining the D 1 signal second binary state during the second clock polarity.
13. The latch of claim 12 wherein the third circuit is a clocked inverter; and,
wherein the fourth circuit is a clocked inverter.
14. A single gate delay latch comprising:
a first circuit having an interface to accept an input signal with a first binary state, an interface to accept a binary clock signal, and an interface to supply a Q signal with a second binary state opposite to the first binary state and delayed by a single gate, the first circuit maintaining the Q signal second binary state during a first clock polarity;
a second circuit having an interface to accept a shadow-Q signal, and interface to accept the clock signal, and an interface to supply the Q signal, the second circuit maintaining the Q signal second binary state during a second clock polarity, opposite to the first polarity; and,
a shadow circuit having an interface to accept the input signal with the first binary state, an interface to accept the clock signal, and an interface to supply the shadow-Q signal, the shadow circuit comprises:
a third circuit having an interface to accept the input signal with the first binary state, an interface to accept the clock signal, and an interface to supply a D 1 signal with the second binary state, delayed by a single gate, the third circuit maintaining the D 1 signal second binary state during the first clock polarity;
an inverter having an input to accept the D 1 signal and an output to supply the shadow-Q signal; and,
a fourth circuit having an interface to accept the shadow-Q signal, and interface to accept the clock signal, and an interface to supply the D 1 signal, the fourth circuit maintaining the D 1 signal second binary state during the second clock polarity.
15. The latch of claim 14 wherein the first circuit is a clocked inverter and the second circuit is a clocked inverter.
16. The latch of claim 14 wherein the third circuit is a clocked inverter and the fourth circuit is a clocked inverter.
17. A master-slave flip-flop comprising:
the single gate delay master latch of claim 14 series-connected to a single gate delay slave-driver, the master latch having a D input to accept a binary first signal with a first polarity; and,
regardless of spurious signals received at the slave latch output, a means for maintaining the first signal first polarity at the slave-driver output until a subsequent clock signal is received.