Patent Assignment
Reel/Frame 042176/0185
Merger and Change of Name
Recorded: 2017-04-06
Pages: 10
Assignors
APPLIED MICRO CIRCUITS CORPORATION
Executed: 2017-01-26
MACOM CONNECTIVITY SOLUTIONS, LLC
Executed: 2017-01-27
MACOM CONNECTIVITY SOLUTIONS, LLC
Executed: 2017-01-26
Assignee
MACOM CONNECTIVITY SOLUTIONS, LLC
C/O MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC, 100 CHELMSFORD STREET, LOWELL, MASSACHUSETTS, 01851
Covered Properties
(167)
Calibration of High-Speed Interleaved Arrays
PCT:
PCT/US2015/037597 ↗
Implementation of Load Acquire/Store Release Instructions Using Load/Store Operation with Dmb Operation
PCT:
PCT/US2015/041322 ↗
Flow Pinning in a Server on a Chip
PCT:
PCT/US2015/041911 ↗
Hazard Prediction for a Group of Memory Access Instructions Using a Buffer Associated with Branch Prediction
PCT:
PCT/US2015/042199 ↗
Programmable Gain Amplifier with Controlled Gain Steps
PCT:
PCT/US2015/042587 ↗
Duplex Transmission Over Reduced Pairs of Twinax Cables
PCT:
PCT/US2015/042589 ↗
Product Coded Modulation Scheme Based on Leech Lattice and Binary and Nonbinary Codes
PCT:
PCT/US2015/042591 ↗
Generating a Timeout Signal Based on a Clock Counter Associated with a Data Request
PCT:
PCT/US2015/042592 ↗
High Frequency Voltage Supply Monitor
PCT:
PCT/US2015/042593 ↗
Systems and Methods Facilitating Multi-Word Atomic Operation Support for System on Chip Environments
PCT:
PCT/US2015/042595 ↗
Main Memory Prefetch Operation and Multiple Prefetch Operations
PCT:
PCT/US2015/042596 ↗
Priority Framework for a Computing Device
PCT:
PCT/US2015/042598 ↗
Generating and/or Employing a Descriptor Associated with a Memory Translation Table
PCT:
PCT/US2015/042600 ↗
Multi-Rate Transmissions Over Twinax Cables
PCT:
PCT/US2015/042789 ↗
Systems and Methods Facilitating Reduced Latency via Stashing in Systems on Chips
PCT:
PCT/US2015/042791 ↗
Prefetch Tag for Eviction Promotion
PCT:
PCT/US2015/042792 ↗
Calibration and Tracking of Receiver
PCT:
PCT/US2015/042795 ↗
Split Loop Timing Recovery
PCT:
PCT/US2015/042797 ↗
High Efficiency Half-Cross-Coupled Decoupling Capacitor
PCT:
PCT/US2015/042798 ↗
Package Programmable Decoupling Capacitor Array
PCT:
PCT/US2016/048857 ↗
Self-Referenced on-Die Voltage Droop Detector
PCT:
PCT/US2017/022022 ↗
Clock and Data Recovery Scheme for Multi-Channel Data Communications Receivers
Patent:
6,307,906 →
Application:
09/168,028 →
Self-Synchronous Data Scrambler
Patent:
6,952,480 →
Application:
09/399,502 →
System and Method for Segmenting a Multidimensional Digital Frame Structure
Patent:
6,961,350 →
Application:
09/745,370 →
System and Method for Programming the Value of Frame Synchronization Words in a Multidimensional Digital Frame Structure
Patent:
6,973,099 →
Application:
09/745,655 →
System and Method for Programming the Location of Frame Synchronization Words in a Multidimensional Digital Frame Structure
Patent:
6,973,100 →
Application:
09/746,490 →
System and Method for Programming the Bit Error Rate of Frame Synchronization Words in a Multidimensional Digital Frame Structure
Patent:
6,965,618 →
Application:
09/747,380 →
Method and Apparatus for Improving Data Integrity and Desynchronizer Recovery Time After a Loss of Signal
Flexible Tributary Interface with Serial Control Line
Timer with Network Synchronized Time Base
Selectable Loss of Signal (Los) Criteria
Maximum Likelihood Channel Estimator
Receiver Signal Strength Indicator
System and Method for Signal Level Detection
Polarization Control for Multichannel and Polarization Multiplexed Optical Transport Networks
Patent:
7,603,044 →
Application:
12/327,753 →
Ethernet Phy Level Security
Parallel Forward Error Correction with Syndrome Recalculation
System and Method for Photo-Image Discovery and Storage
Application:
12/431,914 →
Publication:
US 2010/0277597
System and Method for Virtual Kiosk Stored Photo-image Reproduction
Application:
12/432,559 →
Publication:
US 2010/0281424
System and Method for Photo-image Uplink Confirmation
Application:
12/432,625 →
Publication:
US 2010/0280992
System and Method for Photo-Image Local Distribution
Integrated Circuit Thermally Induced Noise Analysis
System-On-Chip Queue Status Power Management
Flexible Tributary Interface
Multichannel Polarization Control for Polarization Multiplexed Optical Transport Networks
System and Method for Laser Patterning an Integrated Circuit Etching Mask
Patent:
8,394,244 →
Application:
12/566,600 →
System-On-Chip with Feedback Loop for Processor Frequency Control
Patent:
8,868,956 →
Application:
12/639,064 →
System and Method for In-Situ Inspection During Metallurgical Cross-Sectioning
Patent:
8,506,355 →
Application:
12/651,798 →
System-On-Chip with Thermal Management Core
Patent:
8,786,449 →
Application:
12/687,817 →
Operating System with Hardware-Enabled Task Manager for Offloading Cpu Task Scheduling
Patent:
8,881,161 →
Application:
12/695,953 →
Distributed File System with Client-Side Deduplication Capacity
Patent:
8,402,250 →
Application:
12/699,690 →
Signal Level Detection Method
System and Method for Encoding Using Common Partial Parity Products
Patent:
8,347,169 →
Application:
12/714,741 →
System-on-Chip with Memory Speed Control Core
Patent:
8,438,358 →
Application:
12/729,210 →
Multi-Processor System-On-Chip with Dynamic Packet Processing Load Control
Application:
12/756,128 →
System-on-Chip with Dynamic Memory Module Switching
Patent:
8,607,023 →
Application:
12/763,110 →
Frequency Optimization Using Useful Skew Timing
Patent:
8,539,413 →
Application:
12/767,894 →
Dual-Connect Service Box with Router Bypass
Patent:
8,488,618 →
Application:
12/769,540 →
Packet Processing with Dynamic Load Balancing
Patent:
9,158,713 →
Application:
12/772,832 →
Dynamic Memory Module Switching with Read Prefetch Caching
Patent:
8,806,140 →
Application:
12/784,542 →
System and Method for Attached Storage Stacking
Patent:
8,499,012 →
Application:
12/818,870 →
Network-Attached Storage (Nas) Bandwidth Manager
Patent:
8,793,334 →
Application:
12/839,225 →
Carrier Frequency Offset and Doppler Frequency Estimation and Correction for Ofdma and Sc-Fdma
Patent:
8,416,759 →
Application:
12/848,043 →
System and Method for Integrated Circuit Die Size Reduction
Patent:
8,762,915 →
Application:
12/884,264 →
System-On-Chip with Management Module for Controlling Processor Core Internal Voltages
Patent:
8,635,470 →
Application:
12/900,828 →
System and Method for Packet Splitting
Patent:
8,732,351 →
Application:
12/917,425 →
Multistage Latch-Based Isolation Cell
Patent:
8,575,984 →
Application:
12/945,378 →
Multi-Input Iir Filter with Error Feedback
System and Method for Residence Time Calculation
Patent:
8,670,466 →
Application:
12/975,500 →
Zero-Copy Direct Memory Access (DMA) Network-Attached Storage (NAS) File System Block Writing
Patent:
9,092,426 →
Application:
12/983,391 →
System-on-Chip with Power-Save Mode Processor
Patent:
8,832,483 →
Application:
13/014,616 →
Single Carrier-Frequency-Division Multiple Access (Sc-Fdma) Physical Uplink Control Channel (Pucch) 1/1A/1B Detection
Patent:
8,897,118 →
Application:
13/023,641 →
Method and System for Queuing a Request by a Processor to Access a Shared Resource and Granting Access in Accordance with an Embedded Lock Id
Patent:
8,918,791 →
Application:
13/045,453 →
Shadow Latch
Patent:
8,618,856 →
Application:
13/077,949 →
Single Carrier-Frequency-Division Multiple Access (Sc-Fdma) Physical Uplink Control Channel (Pucch) 2/2A/2B Detection
Patent:
8,848,686 →
Application:
13/080,888 →
Threshold Controlled Limited Out of Order Load Execution
Patent:
8,949,581 →
Application:
13/103,833 →
Cut-Through Packet Stream Encryption/Decryption
Patent:
8,838,999 →
Application:
13/109,620 →
System and Method for Selecting a Power Supply Source
Patent:
8,772,966 →
Application:
13/110,162 →
System and Method for Adaptively Configuring an L2 Cache Memory Mesh
Patent:
8,706,966 →
Application:
13/115,029 →
Pass Gate Shadow Latch
Patent:
8,497,721 →
Application:
13/160,569 →
Stashing System and Method for the Prevention of Cache Thrashing
Patent:
8,429,315 →
Application:
13/167,783 →
System and Method for Partitioning Resources in a System-on-Chip (SoC)
Patent:
8,893,267 →
Application:
13/212,112 →
Uplink Single Carrier Frequency Division Multiple Access Multiple-Input Multiple-Output Soft Interference Cancellation Receiver
Patent:
8,665,693 →
Application:
13/212,572 →
Hazard-Free Minimal-Latency Flip-Flop (Hfml-Ff)
Patent:
8,421,514 →
Application:
13/225,044 →
Symmetric Diagonal Interleaving and Encoding/Decoding Circuit and Method
Patent:
8,650,464 →
Application:
13/225,337 →
Load Store Unit With Load Miss Result Buffer
Patent:
8,806,135 →
Application:
13/250,481 →
Outstanding Load Miss Buffer with Shared Entries
Patent:
8,850,121 →
Application:
13/250,544 →
Load Miss Result Buffer With Shared Data Lines
Patent:
8,793,435 →
Application:
13/250,596 →
System and Method for Updating a Data Structure
Patent:
8,762,362 →
Application:
13/278,701 →
System and Method for Controlling Updates of a Data Structure
Patent:
8,898,204 →
Application:
13/278,753 →
System and Method for Searching a Data Structure
Patent:
9,152,661 →
Application:
13/278,785 →
System and Method for the Aggregation of 10GBASE-R Signals into Pseudo 100GBASE-R Signals
Patent:
8,761,209 →
Application:
13/285,562 →
Full Duplex Wire-Line Transceiver with Echo Cancellation Line Driver
Patent:
8,737,278 →
Application:
13/298,580 →
Method for Converting a Single Channel Hardware Module into a Multi-Channel Module
Patent:
8,607,181 →
Application:
13/367,753 →
Packet Forwarding System and Method Using Patricia Trie Configured Hardware
Patent:
8,767,757 →
Application:
13/396,711 →
System and Method for Pre-Fetching Data Based on a Fifo Queue of Packet Messages Reaching a First Capacity Threshold
Patent:
9,336,162 →
Application:
13/398,679 →
Pseudo Single-Phase Flip-Flop (Psp-Ff)
Patent:
8,604,854 →
Application:
13/412,679 →
Optimized Chromatic Dispersion Filter
Patent:
8,792,789 →
Application:
13/413,705 →
Latch Isolation Circuit
Patent:
8,786,319 →
Application:
13/422,755 →
Method and Apparatus for Performing Table Lookup
Patent:
9,058,284 →
Application:
13/422,979 →
Linear Source Follower Amplifier
Patent:
8,742,849 →
Application:
13/437,154 →
Network Synchronized Time Base Timer
Chromatic Dispersion Pre-Compensation
Patent:
8,909,061 →
Application:
13/461,847 →
System and Method for Scaling Total Client Capacity with a Standard-Compliant Optical Transport Network (OTN)
Patent:
9,231,721 →
Application:
13/536,841 →
Managing Requests to Open and Closed Banks in a Memory System
Collimated Beam Channel with Four Lens Optical Surfaces
Self-Test Design for Serializer / Deserializer Testing
Imaging System for Passive Alignment of Engines
Programmable Resistance-Modulated Write Assist for a Memory Device
System and Method for Sata Virtualization and Domain Protection
Systems and Methods for Queue Request Ordering Without Stalling Requests in Aliasing Conditions by Using a Hash Indexed Based Table
Broadcast Messaging and Acknowledgment Messaging for Power Management in a Multiprocessor System
Debugging Processor Hang Situations Using an External Pin
Processor Hang Detection and Recovery
Dynamic Power Control
Cache Miss Detection Filter
End-To-End Flow Control in System on Chip Interconnects
Address Index Recovery Using Hash-Based Exclusive Or
Reformating a Plurality of Signals to Generate a Combined Signal Comprising a Higher Data Rate Than a Data Rate Associated with the Plurality of Signals
Mapping a Plurality of Signals to Generate a Combined Signal Comprising a Higher Data Rate Than a Data Rate Associated with the Plurality of Signals
Tcp Segmentation Offload in a Server on a Chip
Defect Propagation of Multiple Signals of Various Rates When Mapped into a Combined Signal
Allocation of Load Instruction(S) to a Queue Buffer in a Processor System Based on Prediction of an Instruction Pipeline Hazard
Programmable Gain Amplifier with Controlled Gain Steps
Calibration of High-Speed Interleaved Arrays
Patent:
9,071,262 →
Application:
14/162,899 →
Flow Pinning in a Server on a Chip
Duplex Transmission Over Reduced Pairs of Twinax Cables
Generating a Timeout Signal Based on a Clock Counter Associated with a Data Request
Hazard Prediction for a Group of Memory Access Instructions Using a Buffer Associated with Branch Prediction
High Frequency Voltage Supply Monitor
Identification Codewords for a Rate-Adapted Version of a Data Stream
Patent:
9,088,403 →
Application:
14/222,913 →
Implementation of Load Acquire/Store Release Instructions Using Load/Store Operation with Dmb Operation
Application:
14/243,949 →
Publication:
US 2015/0317158
Systems and Methods Facilitating Multi-Word Atomic Operation Support for System on Chip Environments
Data Dependent Jitter Reduction of Switch Driver Signals in High Speed Current Steering Digital-to-Analog Converters
Patent:
9,059,723 →
Application:
14/466,316 →
Multi-Rate Transmissions Over Twinax Cables
High Speed Transceiver Based on Embedded Leech Lattice Constellation
Patent:
9,172,578 →
Application:
14/466,334 →
High Speed Transceiver Based on Concatenates of a Leech Lattice with Binary and Nonbinary Codes
Patent:
8,989,283 →
Application:
14/466,347 →
Product Coded Modulation Scheme Based on Leech Lattice and Binary and Nonbinary Codes
Patent:
9,467,177 →
Application:
14/466,355 →
Concatenates of an E8 Lattice with Binary and Non Binary Codes
Patent:
9,991,907 →
Application:
14/466,361 →
Priority Framework for a Computing Device
Generating a Pulse Clock Signal Based on a First Clock Signal and a Second Clock Signal
Patent:
9,385,696 →
Application:
14/497,629 →
Flexible and Robust Power Grid Connectivity
Patent:
9,761,521 →
Application:
14/519,271 →
Generating and/or Employing a Descriptor Associated with a Memory Translation Table
Main Memory Prefetch Operation and Multiple Prefetch Operation
Prefetch Tag for Eviction Promotion
Split Loop Timing Recovery
Patent:
9,397,822 →
Application:
14/736,754 →
Calibration and Tracking of Receiver
Patent:
9,485,039 →
Application:
14/736,874 →
High Efficiency Half-Cross-Coupled Decoupling Capacitor
Patent:
9,438,225 →
Application:
14/736,882 →
Systems and Methods Facilitating Reduced Latency via Stashing in System on Chips
Package Programmable Decoupling Capacitor Array
Multiple-Queue Integer Coalescing Mapping Algorithm with Shared Based Time
Patent:
9,965,419 →
Application:
15/015,338 →
Gain Calibration by Applying a Portion of an Input Voltage to Voltage Associated with a Capacitor Array
Patent:
9,602,119 →
Application:
15/018,984 →
Metastability Error Reduction in Asynchronous Successive Approximation Analog to Digital Converter
Patent:
9,621,179 →
Application:
15/067,293 →
Self-Referenced on-Die Voltage Droop Detector
Data Managment for Cache Memory
Patent:
9,798,672 →
Application:
15/098,573 →
High Speed Serializer Using Quadrature Clocks
Mimcap Creation and Utilization Methodology
Patent:
9,876,007 →
Application:
15/149,244 →
Efficient Techniques for Process Variation Reduction for Static Timing Analysis
Patent:
10,318,696 →
Application:
15/149,249 →
Split Loop Timing Recovery
Managing a Data Packet for an Operating System Associated with a Multi-Node System
Patent:
10,819,783 →
Application:
15/250,966 →
Clock Control Based on Voltage Associated with a Microprocessor
Patent:
10,348,281 →
Application:
15/256,787 →
Memory Page Request for Optimizing Memory Page Latency Associated with Network Nodes
Patent:
10,439,960 →
Application:
15/351,477 →
Optimizing Memory Mapping(S) Associated with Network Nodes
Write Assist for Memories with Resistive Bit Lines
Method to Dynamically Inject Errors in a Repairable Memory on Silicon and a Method to Validate Built-in-Self-Repair Logic
Techniques for Statistical Frequency Enhancement of Statically Timed Designs
Variation Immune on-Die Voltage Droop Detector
Patent:
10,162,373 →
Application:
15/444,478 →
Related Assignments
(5)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jun 24, 2011
From: CHUDGAR, KEYUR; SATHE, SATISH
To: APPLIED MICRO CIRCUITS CORPORATION
Reel/Frame 026492/0972 →
Security Interest
May 11, 2017
From: MACOM CONNECTIVITY SOLUTIONS, LLC (SUCCESSOR TO APPLIED MICRO CIRCUITS CORPORATION)
To: GOLDMAN SACHS BANK USA, AS COLLATERAL AGENT
Reel/Frame 042444/0891 →
Release of Security Interest
Oct 31, 2017
From: GOLDMAN SACHS BANK USA, AS COLLATERAL AGENT
To: MACOM CONNECTIVITY SOLUTIONS, LLC (SUCCESSOR TO APPLIED MICRO CIRCUITS CORPORATION)
Reel/Frame 044652/0609 →
Assignment of Assignor's Interest
Nov 21, 2017
From: MACOM CONNECTIVITY SOLUTIONS, LLC
To: PROJECT DENVER INTERMEDIATE HOLDINGS LLC
Reel/Frame 044798/0599 →
Change of Name
Dec 6, 2017
From: PROJECT DENVER INTERMEDIATE HOLDINGS LLC
To: AMPERE COMPUTING LLC
Reel/Frame 044717/0683 →