IP Library Granted Patent US 10,972,390
Granted Patent B2
US 10,972,390 · App. 14/045,065 · Granted Apr 6, 2021

TCP segmentation offload in a server on a chip

Inventors: Keyur Chudgar (San Jose, CA); Kumar Sankaran (San Jose, CA)
Assignee: Ampere Computing LLC
H04L45/74H04L47/34H04L47/41H04L47/50H04L69/166
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Quick Facts
Patent No.
US 10,972,390
App. No.
14/045,065
Granted
Apr 6, 2021
Kind
B2
Abstract

A system and method are provided for performing transmission control protocol segmentation on a server on a chip using coprocessors on the server chip. A system processor manages the TCP/IP stack and prepares a large (64 KB) single chunk of data to be sent out via a network interface on the server on a chip. The system software processes this and calls the interface device driver to send the packet out. The device driver, instead of sending the packet out directly on the interface, calls a coprocessor interface and delivers some metadata about the chunk of data to the interface. The coprocessor segments the chunk of data into a maximum transmission unit size associated with the network interface and increments a sequential number field in the header information of each packet before sending the segments to the network interface.

Claims (30)

1. A server on a chip, comprising:

a plurality of coprocessors that segment batches of data in parallel;

a system processor configured for storing a batch of data in a memory and generating header information specifying an IP address for the batch of data and a size of the batch of data;

wherein a coprocessor of the plurality of coprocessors is configured for receiving the header information and splitting the batch of data into a plurality of segments, wherein a size of a segment is based on a maximum transmission unit size of a network interface, and wherein the coprocessor of the plurality of coprocessors is further configured for attaching the header information to the segments and adjusting a sequential number field of the header information based on the plurality of segments;

a queue manager configured for sending the segments to the address specified in the header information and further configured for facilitating communication between the plurality of coprocessors;

a device driver configured for forwarding header information associated with the batch of data from the memory to the coprocessor in response to receiving a device driver call from the system processor, wherein the device driver forwards the header information to the coprocessor via the queue manager;

wherein the system processor, the plurality of coprocessors, the queue manager, and the device driver reside on a single chip.

2. The server of claim 1 , wherein the queue manager routes the segments to a network port on the server based on the address specified.

3. The server of claim 1 , wherein the header information comprises at least one of an Ethernet header, transmission control protocol header, or an internet protocol header.

4. The server of claim 3 , wherein each of the headers comprise distinct sequential number fields.

5. The server of claim 4 , wherein a transmission control protocol header sequential number field is incremented per segment, and an internet protocol header sequential number field is incremented per packet.

6. The server of claim 1 , wherein the segments are a packet of data.

7. The server of claim 1 , wherein the coprocessor is further configured for gathering a plurality of batches of data and sending them as a packet of data.

8. The server of claim 1 , wherein the sequential number field of the header information indicates a total number of segments and a sequence number of each of the segments.

9. A computer implemented method, comprising:

storing, by a system processor, a batch of data in a memory and generating header information that specifies a size of the batch of data and an IP address associated with a destination of the batch of data;

segmenting, by a plurality of coprocessors residing on a single chip along with the system processor, batches of data in parallel, wherein the segmenting comprises:

receiving, by a coprocessor of the plurality of coprocessors, the header information;

splitting, by the coprocessor, the batch of data into a plurality of segments, wherein a size of a segment is based on a maximum transmission unit size of a network interface; and

attaching, by the coprocessor, the header information to each of the plurality of segments and incrementing a sequential number field of the header information based on the number of segments;

directing, by a queue manager residing on the single chip, the segments to a network port based on the IP address specified in the header information;

forwarding, by a device driver residing on the single chip, header information associated with the batch of data from the memory to a coprocessor in response to receiving a device driver call from the system processor, wherein the device driver forwards the header information to the coprocessor via the queue manager; and

receiving, by the plurality of coprocessors, a queue message comprising information about where the batch of data is located, a length of the batch of data, the size of the batch of data or a destination of the batch of data.

10. The method of claim 9 , the segmenting further comprising:

determining, by the coprocessor, the maximum transmission unit size based on the network port associated with the IP address specified in the header information.

11. The method of claim 9 , the segmenting further comprising:

incrementing a transmission control protocol header sequential number field of the header information per segment; and

incrementing an internet protocol header sequential number field of the header information per packet.

12. The method of claim 9 , the segmenting further comprising:

sending a plurality of batches of data as a packet of data.

Assignments (5)
CHANGE OF NAME Recorded Dec 6, 2017
From: PROJECT DENVER INTERMEDIATE HOLDINGS LLC
To: AMPERE COMPUTING LLC
Reel/Frame 044717/0683 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2017
From: MACOM CONNECTIVITY SOLUTIONS, LLC
To: PROJECT DENVER INTERMEDIATE HOLDINGS LLC
Reel/Frame 044798/0599 →
RELEASE OF SECURITY INTEREST Recorded Oct 31, 2017
From: GOLDMAN SACHS BANK USA, AS COLLATERAL AGENT
To: MACOM CONNECTIVITY SOLUTIONS, LLC (SUCCESSOR TO APPLIED MICRO CIRCUITS CORPORATION)
Reel/Frame 044652/0609 →
MERGER AND CHANGE OF NAME Recorded Apr 6, 2017
From: APPLIED MICRO CIRCUITS CORPORATION; MACOM CONNECTIVITY SOLUTIONS, LLC; MACOM CONNECTIVITY SOLUTIONS, LLC
To: MACOM CONNECTIVITY SOLUTIONS, LLC
Reel/Frame 042176/0185 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 3, 2013
From: CHUDGAR, KEYUR; SANKARAN, KUMAR
To: APPLIED MICRO CIRCUITS CORPORATION
Reel/Frame 031337/0413 →