IP Library Granted Patent US 9,424,205
Granted Patent B2
US 9,424,205 · App. 13/742,767 · Granted Aug 23, 2016

System and method for SATA virtualization and domain protection

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Quick Facts
Patent No.
US 9,424,205
App. No.
13/742,767
Granted
Aug 23, 2016
Kind
B2
Abstract

A hardware SATA virtualization system without the need for backend and frontend drivers and native device drivers is disclosed. A lightweight SATA virtualization handler can run on a specialized co-processor and manage requests enqueued by individual guest devices or virtual machines (VMs). The lightweight SATA virtualization handler can also perform the scheduling or queuing of the requests based on performance optimizations to reduce seek time as well as based on the priority of the requests. The specialized co-processor can communicate to an integrated SATA controller through an advanced host controller interface (“AHCI”) data structure that is built by the coprocessor and has commands from one or more VMs. Guest devices or guest operating systems can build associated AHCI data structures in memory, which may be on-chip memory or DDR memory.

Claims (31)

1. A system, comprising:

a memory configured for storing a data structure associated with a guest device;

a coprocessor, communicably coupled to the memory, configured for interfacing between the guest device and a SATA controller; and

a bus fabric configured for redirecting a SATA controller access from the guest device to a corresponding address in the data structure, wherein the coprocessor is further configured for performing an address translation for the access and forwarding the translated access via the bus fabric to the SATA controller.

2. The system of claim 1 , wherein the bus fabric allows a SATA controller access originating from the coprocessor to proceed.

3. The system of claim 1 , further comprising a memory management unit configured for storing address translation tables, and linking a physical address to a corresponding virtual address and an intermediate physical address.

4. The system of claim 3 , wherein the memory management unit is configured for receiving memory accesses from the SATA controller and diverting the memory accesses to a physical address corresponding to an appropriate virtual address.

5. The system of claim 1 , further comprising a queue manager configured for receiving command header requests from the guest device and storing them in a queue in the queue manager.

6. The system of claim 5 , wherein the coprocessor is configured for translating addresses and forwarding translated accesses to the SATA controller in an order that is based on the queue in the queue manager.

7. The system of claim 5 , wherein the command header requests are associated with a source domain ID that identifies the guest device from which each command header request originated.

8. The system of claim 7 , wherein the SATA controller is configured for checking whether a command header request has access permission based on the source domain ID, and is further configured for generating an error notification in response to a command header request lacking permission.

9. The system of claim 1 , wherein the memory is at least one of DDR memory or on-chip memory.

10. The system of claim 9 , wherein in response to the guest device storing the data structure in DDR memory, the coprocessor is configured for copying a portion of the data structure to an on-chip memory.

11. The system of claim 1 , wherein the coprocessor is configured for building a consolidated data structure in the memory based on data structures associated with a plurality of guest devices.

12. A method, comprising:

storing an advanced host controller interface data structure in a memory, wherein the data structure is associated with a guest operating system;

redirecting a SATA controller access to the data structure in response to the SATA controller access originating from the guest operating system;

translating an address for the access; and

forwarding the translated access via a bus fabric to the SATA controller.

13. The method of claim 12 , further comprising:

receiving an access from the SATA controller; and

translating an address of the access received from the SATA controller to a physical address that corresponds to a specific virtual address.

14. The method of claim 12 , further comprising building a consolidated data structure in the memory based on data structures associated with a plurality of guest operating systems.

15. The method of claim 12 , further comprising copying a subset of the data structure to on-chip memory in response to the data structure being stored in DDR memory.

16. The method of claim 12 , further comprising receiving a command header request from the guest operating system and storing the command header request in a queue.

17. The method of claim 16 , further comprising translating addresses of a plurality of accesses and forwarding the translated plurality of accesses to the SATA controller in an order based on the queue.

18. The method of claim 16 , further comprising identifying the guest operating system that the command header request originated from based on a source domain ID associated with the command header request.

19. The method of claim 18 , further comprising:

determining whether the command header request has access permission based on the source domain ID;

executing an associated command in response to the command header request having permission; and

generating an error in response to the command header request not having permission.

Assignments (3)
SECURITY INTEREST Recorded May 11, 2017
From: MACOM CONNECTIVITY SOLUTIONS, LLC (SUCCESSOR TO APPLIED MICRO CIRCUITS CORPORATION)
To: GOLDMAN SACHS BANK USA, AS COLLATERAL AGENT
Reel/Frame 042444/0891 →
MERGER AND CHANGE OF NAME Recorded Apr 6, 2017
From: APPLIED MICRO CIRCUITS CORPORATION; MACOM CONNECTIVITY SOLUTIONS, LLC; MACOM CONNECTIVITY SOLUTIONS, LLC
To: MACOM CONNECTIVITY SOLUTIONS, LLC
Reel/Frame 042176/0185 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 16, 2013
From: MARULKAR, RAJENDRA SADANANAD; SATHE, SATISH; CHUDGAR, KEYUR
To: APPLIED MICRO CIRCUITS CORPORATION
Reel/Frame 029640/0747 →