Optimizing memory mapping(s) associated with network nodes
Various aspects provide for optimizing memory mappings associated with network nodes. For example, a system can include a first network node and a second network node. The first network node generates a memory page request in response to an invalid memory access associated with a virtual central processing unit of the first network node. The second network node receives the memory page request in response to a determination that the second network node comprises a memory space associated with the memory page request. The first network node also maps a memory page associated with the memory page request based on a set of memory page mappings stored by the first network node.
1. A system for optimizing memory mappings associated with a plurality of network nodes in a multi-node system, comprising:
a first network node of the plurality of nodes configured for generating a memory page request in response to an invalid memory access associated with a virtual central processing unit of the first network node and, in response to a determination that a second network node of the plurality of nodes comprises a memory space associated with the memory page request, transmitting the memory page request to the second network node via a communication channel; and
the second network node configured for receiving the memory page request, retrieving a memory page request associated with the memory page request, and transmitting the memory page to the first network device via the communication channel, the first network node being further configured for mapping a memory page associated with the memory page request based on a set of memory page mappings stored by the first network node.
2. The system of claim 1 , wherein the first network node is configured for modifying a page table entry associated with the memory page during the mapping of the memory page.
3. The system of claim 1 , wherein the first network node comprises a memory configured for storing the set of memory page mappings in response to a determination that an operating system associated with the second network node satisfies a defined criterion.
4. The system of claim 1 , wherein the first network node is configured for mapping, in response to a determination that the first network node comprises the memory space, the memory page associated with the memory page request based on a page table entry address of the memory page.
5. The system of claim 4 , wherein the first network node is configured for modifying a page table entry associated with the page table entry address during the mapping of the memory page.
6. The system of claim 4 , wherein the first network node comprises a memory configured for storing the page table entry address in response to a determination that an operating system associated with the second network node satisfies a defined criterion.
7. The system of claim 1 , wherein the memory space is associated with a guest physical address, and wherein the first network node is configured for mapping a guest physical address page based on a page table entry address stored by the first network node.
8. The system of claim 1 , wherein the first network node is configured for mapping the memory page to a physical address associated with the first network node.
9. The system of claim 1 , wherein the first network node is a first system on a chip (SoC) and the second network node is a second SoC different from the first SoC.
10. A method for optimizing memory mappings associated with a plurality of network nodes in a multi-node system, the method comprising, by a first network node of the plurality of the network nodes:
generating a memory page request in response to an invalid memory access associated with a first network device;
in response to a determination that a second network node of the plurality of network nodes comprises a memory page associated with the memory page request, transmitting the memory page request to the second network node via a communication channel,
receiving, from the second network device and via the communication channel, a memory page associated with the memory page request;
determining a page table entry associated with the memory page based on a set of memory page mappings stored by the first network device; and
performing a memory mapping process associated with the page table entry.
11. The method of claim 10 , wherein the first network node is a first system on a chip (SoC) and the second network node is a second SoC different from the first SoC.
12. The method of claim 10 , wherein the receiving comprises receiving a memory page associated with the memory page request from a memory of the second network device in response to a determination that the memory of the network device comprises a memory space associated with the memory page request.
13. The method of claim 10 , further comprising:
determining whether an operating system associated with the first network device satisfies a defined criterion; and
storing the set of memory page mappings in response to a determination that the operating system satisfies the defined criterion.
14. The method of claim 10 , wherein the determining the page table entry comprises determining the page table entry without performing a page table walk process.
15. The method of claim 10 , wherein the performing the memory mapping process comprises modifying the page table entry.
16. A network device in a multi-device system, the network device comprising:
a memory configured for storing a set of memory page mappings; and
a memory manager configured for:
generating a memory page request in response to an invalid memory access associated with the network device,
in response to a determination that a second network device in the multi-device system comprises a memory page associated with the memory page request, transmitting the memory page request to the second network device via a communication channel,
receiving, from the second network device and via the communication channel, a memory page associated with the memory page request,
determining a page table entry associated with the memory page based on the set of memory page mappings, and
performing a memory mapping process associated with the page table entry.
17. The network device of claim 16 , wherein the first network node is a first system on a chip (SoC) and the second network node is a second SoC different from the first SoC.
18. The network device of claim 16 , wherein the memory manager is configured for storing the set of memory page mappings in the memory in response to a determination that an operating system associated with the network device satisfies a defined criterion.
19. The network device of claim 16 , wherein the memory manager is configured for determining the page table entry based on a hash function associated with a memory address for the memory page.
20. The network device of claim 16 , wherein the memory manager is configured for modifying the page table entry during the memory mapping process.