Granted Patent B2

US 9,213,643 · App. 13/799,268 · Granted Dec 15, 2015

Abstract

Claims (29)

1. A system, comprising:

at least one processing component that comprises a cache controller, the cache controller being configured for managing a cache memory associated with a processor; and

a centralized controller configured for storing a power state of the processor, storing one or more other power states associated with one or more other processors, and communicating with the cache controller based on the power state of the processor.

2. The system of claim 1 , wherein the centralized controller is configured for filtering communication with the cache controller based on the power state of the processor.

3. The system of claim 1 , wherein the centralized controller is configured for sending a snoop message to the cache controller in response to a determination that the processor is in a powered-up state.

4. The system of claim 3 , wherein the cache controller is configured for sending an acknowledgment message to the centralized controller in response to receiving the snoop message.

5. The system of claim 4 , wherein the centralized controller is configured for entering a wait state for the acknowledgment message in response to sending the snoop message.

6. The system of claim 1 , wherein the centralized controller is configured for not sending a snoop message to the cache controller in response to a determination that the processor is in a powered-down state.

7. The system of claim 6 , wherein the centralized controller is configured for implying an acknowledgment message from the cache controller in response to the determination that the processor is in the powered-down state.

8. The system of claim 7 , wherein the centralized controller is configured for receiving a powering-on message when the processor has returned to a powered-on state.

9. The system of claim 1 , wherein the centralized controller is configured for determining the power state of the processor.

10. The system of claim 1 , wherein the cache controller and the centralized controller are coupled to a bus.

11. The system of claim 1 , wherein the centralized controller is configured for associating the at least one processing component with a unique power domain.

12. The system of claim 1 , wherein the at least one processing component comprises the cache controller, the cache memory, and the processor.

13. The system of claim 1 , wherein the centralized controller is configured for implementing a cache coherence protocol.

14. A method, comprising:

determining a power state for a processor;

storing the power state for the processor;

storing one or more other power states associated with one or more other processors; and

communicating with a controller associated with the processor based on the power state of the processor.

15. The method of claim 14 , wherein the communicating comprises sending a snoop message to the controller in response to a determination that the processor is in a powered-up state.

16. The method of claim 15 , wherein the communicating further comprises entering a wait state to wait for a response from the controller.

17. The method of claim 16 , wherein the communicating further comprises receiving an acknowledgment message from the controller.

18. The method of claim 14 , wherein the communicating comprises withholding from sending a snoop message to the controller and implying an acknowledgment message from the controller in response to a determination that the processor is in a powered-down state.

19. A system, comprising:

means for determining a power state for a processor;

means for storing the power state for the processor;

means for storing one or more other power states associated with one or more other processors; and

means for communicating with a controller associated with the processor based on the power state of the processor.

Assignments (6)