High efficiency half-cross-coupled decoupling capacitor
View Patent ↗A decoupling capacitor circuit design facilitates high operational frequency without sacrificing area efficiency. In order to disassociate the sometimes opposing design criteria of high operational frequency and area efficiency, a p-channel field effect transistor (PFET) and an n-channel field effect transistor are connected in a half-cross-coupled (HCC) fashion. The HCC circuit is then supplemented by at least one area efficient capacitance (AEC) device. The half-cross-coupled transistors address the high frequency design requirement, while the AEC device(s) address the high area efficiency requirement. The design eliminates the undesirable trade-off between operating frequency and area efficiency inherent in some conventional DCAP designs.
1. A decoupling capacitor circuit, comprising:
a first p-channel field effect transistor (PFET);
a first n-channel field effect transistor (NFET); and
at least one capacitive device,
wherein
a first PFET source and a first PFET body of the first PFET are connected to a voltage supply,
a first NFET source and a first NFET body of the first NFET are connected to ground,
the at least one capacitive device is connected to at least one of a first PFET gate of the first PFET or a first NFET gate of the first NFET, and
inclusion of the at least one capacitive device increases an area efficiency of the decoupling capacitor circuit without changing a frequency response of the decoupling capacitor circuit.
2. The decoupling capacitor circuit of claim 1 , wherein
a first PFET drain of the first PFET is connected to the first NFET gate of the first NFET, and
a first NFET drain of the first NFET is connected to the first PFET gate of the first PFET.
3. The decoupling capacitor circuit of claim 2 , wherein the at least one capacitive device comprises a second PFET.
4. The decoupling capacitor circuit of claim 3 , wherein
a second PFET drain, a second PFET source, and a second PFET body of the second PFET are connected to the voltage supply, and
a second PFET gate of the second PFET is connected to the first PFET gate of the first PFET.
5. The decoupling capacitor circuit of claim 2 , wherein the at least one capacitive device comprises a second NFET.
6. The decoupling capacitor circuit of claim 5 , wherein
a second NFET drain, a second NFET source, and a second NFET body of the second NFET are connected to ground, and
a second NFET gate of the second NFET is connected to the first NFET gate of the first NFET.
7. The decoupling capacitor circuit of claim 3 , wherein
a second PFET source and a second PFET drain of the second PFET are connected to ground,
a second PFET body of the second PFET is connected to the voltage supply, and
a second PFET gate of the second PFET is connected to the first NFET gate of the first NFET.
8. The decoupling capacitor circuit of claim 5 , wherein
a second NFET drain and a second NFET source of the second NFET are connected to the voltage supply,
a second NFET body of the second NFET is connected to ground, and
a second NFET gate of the second NFET is connected to the first PFET gate of the PFET.
9. The decoupling capacitor circuit of claim 1 , wherein the voltage supply is a voltage supply of a power distribution network.
10. The decoupling capacitor circuit of claim 9 , wherein the decoupling capacitor circuit is an on-chip component of a very-large-scale-integration (VLSI) system that comprises the power distribution network.
11. The decoupling capacitor circuit of claim 9 , wherein the decoupling capacitor circuit is an off-chip component of a very-large-scale-integration (VLSI) system that comprises the power distribution network.
12. A method for suppressing power supply noise, comprising:
connecting a first source and a first body of a first p-channel field effect transistor (PFET) to a voltage supply;
connecting a second source and a second body of an n-channel field effect transistor (NFET) to ground;
connecting a first drain of the first PFET to a first gate of the NFET;
connecting a second drain of the NFET to a second gate of the first PFET;
connecting a third drain, a third source, and a third body of a second PFET to the voltage supply; and
connecting a third gate of the second PFET to the second gate of the first PFET.
13. The method of claim 12 , wherein the NFET comprises a first NFET, and the method further comprises:
connecting a fourth drain, a fourth source, and a fourth body of a second NFET to ground; and
connecting a fourth gate of the second NFET to the first gate of the first NFET.
14. The method of claim 12 , wherein the connecting the first source and the first body of the first PFET to the voltage supply comprises connecting to a voltage supply of a power distribution network.
15. A system for suppressing power supply noise, comprising:
a first p-channel field effect transistor (PFET), wherein a first PFET source and a first PFET body of the first PFET are connected to a voltage supply;
a first n-channel field effect transistor (NFET), wherein a first NFET source and a first NFET body of the first NFET are connected to ground; and
a second NFET,
wherein
a first PFET drain of the first PFET is connected to a first NFET gate of the first NFET,
a first NFET drain of the first NFET is connected to a first PFET gate of the PFET,
a second NFET drain, a second NFET source, and a second NFET body of the second NFET is connected to ground, and
a second NFET gate of the second NFET is connected to the first NFET gate of the first NFET.
16. The system of claim 15 , further comprising a second PFET, wherein
a second PFET drain, a second PFET source, and a second PFET body of the second PFET are connected to the voltage supply, and
a second PFET gate of the second PFET is connected to the first PFET gate of the first PFET.
17. The system of claim 15 , wherein inclusion of the second NFET increases an area efficiency of the system without increasing a channel length of the first PFET and the first NFET.
18. The system of claim 15 , wherein the voltage supply is a voltage supply of a power distribution network of a very-large-scale-integration (VLSI) system.
19. The system of claim 18 , wherein the system is an on-chip component of the VLSI system.
20. The system of claim 18 , wherein the system is an off-chip component of the VLSI system.