System and method for adaptively configuring an L2 cache memory mesh
View Patent ↗A system and method are provided for adaptively configuring L2 cache memory usage in a system of microprocessors. A system-on-chip (SoC) is provided with a plurality of n selectively enabled processor cores and a plurality of n L2 cache memories. The method associates each L2 cache with a corresponding processor core, and shares the n L2 caches between enabled processor cores. More explicitly, associating each L2 cache with the corresponding processor core means connecting each processor core to its L2 cache using an L2 data/address bus. Sharing the n L2 caches with enabled processors means connecting each processor core to each L2 cache via a data/address bus mesh with dedicated point-to-point connections.
1. A method for configuring L2 cache memory usage, the method comprising:
providing a first system-on-chip (SoC) comprising:
a plurality of processor cores;
a plurality of L2 cache memories; and
an input/output (IO) interface connected to an external memory;
associating each L2 cache with a corresponding processor core selected from the plurality of processor cores;
sharing the L2 caches among the plurality of processor cores by connecting each processor core to each L2 cache via a data/address bus mesh with dedicated point-to-point connections; and
transferring information stored in a first L2 cache associated with the first processor core by utilizing processor cores other than the first processing core, to the external memory.
2. The method of claim 1 wherein associating each L2 cache with the corresponding processor core comprises connecting each processor core to its associated L2 cache using an L2 data/address bus.
3. The method of claim 1 further comprising:
a second L2 cache manager associated with an enabled second processor searching an associated second L2 cache for a first message; and,
wherein sharing the L2 caches comprises the second L2 cache manager searching for the first message in another shared L2 cache.
4. The method of claim 3 wherein searching for the first message in another (n−1) shared L2 caches comprises the second L2 cache manager searching the other (n−1) shared L2 caches and searching its associated L2 cache.
5. The method of claim 3 wherein providing the first SoC comprises providing an IO interface connected to an external memory; and wherein the method further comprises:
the second L2 cache manager reading the first message from the external memory while searching another (n−1) shared L2 cache; and,
on finding the first message in an L2 cache, discontinuing the read from the external memory.
6. The method of claim 1 further comprising:
a second L2 cache manager associated with an enabled second processor adding a message to a first L2 cache associated with a disabled first processor core.
7. The method of claim 1 wherein providing the first SoC comprises providing the first SoC with an external IO interface connected to its L2 data/address bus mesh, and providing a second SoC comprising at least one enabled processor core, an associated L2 cache, an L2 data/address bus mesh connected to its L2 cache, and an external IO interface connected to its L2 data/address bus mesh and the IO port of the first SoC; and
wherein sharing the L2 caches comprises sharing the L2 caches of the first and second SoCs with enabled processor cores in the first and second SoCs.
8. The method of claim 7 wherein providing the first SoC includes providing an IO interface connected to an external memory; and wherein the method further comprises:
a second L2 cache manager associated with an enabled second processor searching its associated second L2 cache for a first message;
wherein sharing the plurality of L2 caches comprises the second L2 cache manager searching for the first message in the shared L2 caches of the first and second SoCs;
the method further comprising:
the second L2 cache manager reading the first message from the external memory; and on finding the first message in an L2 cache, discontinuing the read from the external memory.
9. The method of claim 7 further comprising:
a second L2 cache manager, associated with an enabled second processor in the first SoC, adding a message to a first L2 cache associated with a disabled first processor core.
10. A system-on-chip (SoC) comprising:
a first SoC comprising a plurality of processor cores;
a plurality of L2 caches, each L2 cache associated with a corresponding processor core;
a data/address bus mesh with dedicated point-to-point connections between each processor core and each L2 cache;
an input/output (IO) interface connected to an external memory; and
a main data/address bus connecting each processor core to the IO interface, wherein a first L2 cache associated with a first processor core transfers information stored in the first L2 cache by processor cores other than the first processing core, to the external memory.
11. The system of claim 10 wherein each L2 cache comprises a cache manager,
and wherein a second cache manager associated with an enabled second processor searches an associated second L2 cache for a first message, and searches for the first message in another shared L2 cache.
12. The system of claim 11 wherein the second cache manager searches another shared L2 cache and searches its associated L2 cache.
13. The system of claim 11 further comprising:
an IO interface connected to an external memory;
a main data/address bus connecting each processor core to the IO interface;
wherein the second L2 cache manager reads the first message from the external memory while searching another shared L2 cache, and on finding the first message in an L2 cache, discontinues the read from the external memory.
14. The system of claim 10 wherein a second cache, associated with an enabled second processor core, adds a message to a first L2 cache associated with a disabled first processor core.
15. The system of claim 10 further comprising:
a first IO interface connected to the first SoC L2 data/address bus mesh, and connected to an IO interface of a second SoC;
the second SoC comprising at least one enabled processor core, an associated L2 cache, and an L2 data/address bus mesh connected to its L2 cache and its IO interface; and wherein the plurality of L2 caches and the L2 cache associated with the second SoC are shared between enabled processor cores in the first and second SoCs.
16. The system of claim 15 further comprising:
a first SoC second IO interface connected to an external memory;
a first SoC main data/address bus connecting each processor core to the second IO interface;
wherein a second L2 cache associated with an enabled second processor core in the first SoC searches its associated second L2 cache for a first message, searches for the first message in the shared L2 caches of the first and second SoCs while reading the first message from the external memory, and on finding the first message in an L2 cache, discontinues the read from the external memory.
17. The system of claim 15 wherein a second L2 cache associated with an enabled processor core in the first SoC, adds a message to a first L2 cache associated with the first processor core in the second SoC.