System-on-chip with memory speed control core

1. A method for using a system-on-chip (SoC) memory speed control logic core to control memory maintenance and access parameters, the method comprising:

providing an SoC with an internal hardware-enabled memory speed control logic (MSCL) core;

accessing an array of SoC memory control parameter registers;

selecting a set of parameters from one of the registers;

delivering the selected set of parameters to an SoC memory controller, to replace an initial set of parameters;

wherein delivering the selected set of parameters to the SoC memory controller includes the MSCL:

asserting a hold signal, so that no new memory transactions are generated by a processor;

waiting for current memory transactions to complete;

sending a self-refresh command to the memory controller;

writing the selected parameters into the memory controller;

deasserting the self-refresh command; and,

subsequent to deasserting the self-refresh command, commanding the memory controller to perform a memory test, to verify that the off-SoC memory is operational;

if the memory test passes, proceeding to the deassertion of the hold signal; and,

if the memory test fails, then resending the self-refresh command and reinstalling the initial set of parameters;

deasserting the hold signal;

the memory controller managing an off-SoC memory using the delivered set of parameters;

wherein the delivered set of parameters are modified without resetting the system and without losing data in the memory.

2. The method of claim 1 further comprising: accepting a thermal trip memory speed command representing an overheating state; and, wherein selecting the set of parameters from one of the registers includes automatically selecting a thermal cool-down register of default minimum frequency control parameters.

3. The method of claim 1 further comprising: the MSCL accepting an auto-change memory speed command associated with a first one of a plurality of memory operating frequencies; and, wherein selecting the set of parameters from one of the registers includes: the MSCL sending a first parameter select signal to the array memory control parameter registers; selecting a first register in response to the first parameter select signal; and, reading a first set of parameters from the first register associated with the first memory operating frequency.

4. The method of claim 1 wherein accessing the array of SoC memory control parameter registers includes accessing registers with memory control parameters selected from a group consisting of column address strobe (CAS) latency (tAAmin), row address strobe (RAS) to CAS delay (tRCDmin), active to precharge delay time (tRAS min), active to active refresh delay time (tRC min), tCAS, tRP, and combinations of the above-mentioned parameters.

5. The method of claim 1 wherein delivering the selected set of parameters to an SoC memory controller, to replace the initial set of parameters includes delivering a first set of parameters; wherein managing the off-SoC memory using the delivered set of parameters includes: the memory controller operating the off-SoC memory at an initial frequency associated with the initial set of parameters; and, subsequent to receiving the first set of parameters, the memory controller operating the off-SoC memory at a first frequency associated with the first set of parameters, which is different from the initial frequency.

6. A system-on-chip (SoC) with memory speed control logic to control memory maintenance and access parameters, the SoC comprising:

a processor;

an internal hardware-enabled memory speed control logic (MSCL) core having an interface to accept memory speed commands and an interface to supply parameter select commands;

wherein the MSCL has an interface connected to the processor and an interface connected to the memory controller, wherein the MSCL, subsequent to receiving a memory speed change command, asserts a hold signal to the processor, so that no new memory transactions are generated by the processor, and waits for current memory transactions to complete;

an array of memory control parameter registers having an interface to supply a selected a set of parameters from one of the registers; and,

a memory controller having an interface to accept the selected set of parameters from the register array, to replace an initial set of parameters, and an interface connected to an off-SoC memory,

wherein the memory controller receives a self-refresh command from the MSCL, subsequent to the completion of the current memory transactions and prior to receiving the selected parameters from the register array; and, wherein the MSCL deasserts the self-refresh command after the selected parameters are received by the memory controller, and

subsequent to deasserting the self-refresh command, commands the memory controller to perform a memory test, to verify that the off-SoC memory is operational, and if the memory test passes, deasserts the hold signal to the processor, but if the memory test fails, resends the self-refresh command and commands the reinstallation of the initial set of parameters;

deasserts the hold signal to the processor;

the memory controller managing the off-SoC memory using the accepted set of parameters, wherein the set of parameters are modified without resetting the system and without losing data in the memory.

7. The SoC of claim 6 wherein the register array has an interface to accept a thermal trip memory speed command representing an overheating state that automatically triggers the selection of a thermal cool-down register with default minimum frequency control parameters.

8. The SoC of claim 6 wherein the MSCL accepts an auto-change memory speed command associated with a first one of a plurality of memory operating frequencies, and sends a first parameter select signal in response; and, wherein the register array selects a first register in response to the first parameter select signal and reads a first set of parameters from the first register associated with the first memory operating frequency.

9. The SoC of claim 6 wherein register array includes registers with memory control parameters selected from a group consisting of column address strobe (CAS) latency (tAAmin), row address strobe (RAS) to CAS delay (tRCDmin), active to precharge delay time (tRAS rain), active to active refresh delay time (tRC min), tCAS, tRP, and combinations of the above-mentioned parameters.

10. The SoC of claim 6 wherein the register array sends a first set of parameters to the memory controller, replacing the initial set of parameters; and, wherein the memory controller operates the off-SoC memory at an initial frequency associated with the initial set of parameters, and subsequent to receiving the first set of parameters, operates the off-SoC memory] at a first frequency associated with the first set of parameters, which is different from the initial frequency.