Granted Patent B1

US 8,421,514 · App. 13/225,044 · Granted Apr 16, 2013

Abstract

Claims (157)

1. A hazard-free minimal-latency flip-flop (HFML-FF) comprising:

a master latch comprising:

a first relay gate having an input to accept a D 1 signal with a binary value, an input to accept a clock signal, an input to accept an inverted shadow-D 2 signal, and an output to supply a D 2 signal with a binary value equal to a shadow-D 2 binary value, the first relay gate output supplied in response to the D 1 signal, the inverted shadow-D 2 signal, and the clock signal;

a first shadow gate having an input to accept a shadow-D 1 signal, an input to accept the clock signal, and an output to supply a shadow-D 2 signal and the inverted shadow-D 2 signal, the first shadow gate outputs supplied in response to the shadow-D 1 signal and clock signal;

a slave latch comprising:

a second relay gate having an input to accept the D 2 signal, an input to accept the clock signal, an input to accept an inverted shadow-Q signal, and an output to supply a Q signal with a binary value equal to the D 1 and shadow-Q signal binary values, the second relay gate output supplied in response to the D 2 signal, the inverted shadow-Q signal, and the clock signal; and,

a second shadow gate having an input to accept a signal selected from a group consisting of the D 2 signal and the shadow-D 2 signal, an input to accept the clock signal, and an output to supply a shadow-Q signal and the inverted shadow-Q signal, the second shadow gate output supplied in response to the selected D 2 signal and clock signal.

2. The HFML-FF of claim 1 wherein the master latch further comprises:

a first inverter having an input to accept an input D signal with a binary value, and having an output to supply the D 1 signal to the first relay gate and the shadow-D 1 signal to the first shadow gate.

3. The HFML-FF of claim 1 wherein the master latch further comprises:

a first inverter having an input to accept an input D signal with a binary value, and having an output to supply the D 1 signal to the first relay gate; and,

a second inverter having an input to accept the input D signal, and having an output to supply the shadow-D 1 signal to the first shadow gate.

4. The HFML-FF of claim 1 wherein the first relay gate comprises:

a first clocked pass gate circuit having an input to accept the D 1 signal, an input to accept the clock signal, and an output to supply the D 2 signal in a master latch pass mode, the D 2 signal having a binary value equal to the D 1 binary value;

a third inverter to accept the inverted shadow-D 2 signal having a binary value equal to an inverse of the shadow-D 2 signal binary value, and supply a slave D 2 signal having a binary value equal to the D 2 signal binary value; and,

a second clocked pass gate circuit having an input to accept the slave D 2 signal, an input to accept the clock signal, and an output to supply the D 2 signal in a master latch hold mode;

wherein the first shadow gate comprises:

a third clocked pass gate circuit having an input to accept the shadow-D 1 input signal, an input to accept the clock signal, and an output to supply the shadow-D 2 signal in the master latch pass mode;

a fourth inverter having an input to accept the shadow-D 2 signal and an output to supply the inverted shadow-D 2 signal;

a fifth inverter having an input to accept the inverted shadow-D 2 signal and an output to supply a shadow slave D 2 signal having a binary value equal to the D 2 signal binary value; and,

a fourth clocked pass gate circuit having an input to accept the shadow slave D 2 signal, an input to accept the clock signal, and an output to supply the shadow D 2 signal in the master latch hold mode.

5. The HFML-FF of claim 4 wherein the second relay gate comprises:

a fifth clocked pass gate circuit having an input to accept the D 2 signal, an input to accept the clock signal, and an output to supply the Q signal in a slave latch pass mode, the Q signal having a binary value equal to the D 2 binary value;

a sixth inverter to accept the inverted shadow-Q signal having a binary value equal to an inverse of the shadow-Q signal, and supply a slave Q signal with a binary value equal to the Q signal binary value; and,

a sixth clocked pass gate circuit having an input to accept the slave Q signal, an input to accept the clock signal, and an output to supply the Q signal in a slave latch hold mode;

wherein the second shadow gate comprises:

a seventh clocked pass gate circuit having an input to accept the selected D 2 input signal, an input to accept the clock signal, and an output to supply the shadow-Q signal in the slave latch pass mode;

a seventh inverter having an input to accept the shadow-Q signal and an output to supply the inverted shadow-Q signal;

an eighth inverter having an input to accept the inverted shadow-Q signal and an output to supply a shadow slave Q signal having a binary value equal to the Q signal binary value; and,

an eighth clocked pass gate circuit having an input to accept the shadow slave Q signal, an input to accept the clock signal, and an output to supply the shadow-Q signal in the slave latch hold mode.

6. The HFML-FF of claim 4 wherein the first clocked pass gate circuit comprises:

a first PMOS field effect transistor (FET) having a first source/drain (S/D) connected to the D 1 input signal, a second S/D connected to supply the D 2 signal, and a gate connected to receive a second clock signal (CK 2 ) having the same binary value as a clock signal (CLK) and with a second delay with respect to CLK;

a first NMOS FET having a first S/D connected to the first S/D of the first PMOS FET, a second S/D connected to the second S/D of the first PMOS FET, and a gate to receive a third clock signal (CK 3 ) equal to an inverted CLK binary value, and with a third delay with respect to CLK, greater than the second delay;

wherein the second clocked pass gate circuit comprises:

a second PMOS FET having a first S/D connected to receive the slave D 2 signal, a second S/D to supply the D 2 signal, and a gate connected to receive a first clock signal (CK 1 ) equal to the inverted CLK binary value, and with a first delay with respect to CLK, less than the second delay;

a second NMOS FET having a first S/D connected to the first S/D of the second PMOS FET, a second S/D connected to the second S/D of the second PMOS FET, and a gate to receive CLK;

wherein the third clocked pass gate circuit comprises:

a third PMOS FET having a first SD connected to the shadow D 1 signal, a second S/D connected to supply the shadow-D 2 signal, and a gate connected to receive CK 2 ;

a third NMOS FET having a first S/D connected to the first S/D of the third PMOS FET, a second S/D connected to the second S/D of the third PMOS FET, and a gate to receive CK 3 ;

wherein the fourth clocked pass gate circuit comprises:

a fourth PMOS FET having a first S/D connected to receive the shadow slave D 2 signal, a second S/D to supply the shadow-D 2 signal, and a gate connected to receive CK 1 ;

a fourth NMOS FET having a first S/D connected to the first S/D of the fourth PMOS FET, a second S/D connected to the second S/D of the fourth PMOS FET, and a gate to receive CLK.

7. The HFML-FF of claim 6 wherein the fifth clocked pass gate circuit comprises:

a fifth PMOS FET having a first source/drain (S/D) connected to the D 2 input signal, a second S/D connected to supply the Q signal, and a gate connected to receive CK 1 ;

a fifth NMOS FET having a first S/D connected to the first S/D of the fifth PMOS FET, a second S/D connected to the second S/D of the fifth PMOS FET, and a gate to receive CLK;

wherein the sixth clocked pass gate circuit comprises:

a sixth PMOS FET having a first S/D connected to receive the slave Q signal, a second S/D to supply the Q signal, and a gate connected to receive CLK;

a sixth NMOS FET having a first S/D connected to the first S/D of the sixth PMOS FET, a second S/D connected to the second S/D of the sixth PMOS FET, and a gate to receive CK 1 ;

wherein the seventh clocked pass gate circuit comprises:

a seventh PMOS FET having a first SD connected to the selected D 2 signal, a second S/D connected to supply the shadow-Q signal, and a gate connected to receive CK 1 ;

a seventh NMOS FET having a first S/D connected to the first S/D of the seventh PMOS FET, a second S/D connected to the second S/D of the seventh PMOS FET, and a gate to receive CLK;

wherein the eighth clocked pass gate circuit comprises:

an eighth PMOS FET having a first S/D connected to receive the shadow slave Q signal, a second S/D to supply the shadow-Q signal, and a gate connected to receive CLK;

an eighth NMOS FET having a first S/D connected to the first S/D of the eighth PMOS FET, a second S/D connected to the second S/D of the eighth PMOS FET, and a gate to receive CK 1 .

8. The HFML-FF of claim 1 wherein the first relay gate comprises:

a first clocked inverter circuit having an input to accept the D 1 signal, an input to accept the clock signal, and an output to supply the D 2 signal in a master latch pass mode, where the D 2 signal has a binary value equal to an inverted D 1 signal binary value;

a second clocked inverter circuit having an input to accept an inverted shadow-D 2 signal with a binary value equal to an inverse of the D 2 signal binary value, an input to accept the clock signal, and an output to supply the D 2 signal in a master latch hold mode;

wherein the first shadow gate comprises:

a third clocked inverter circuit having an input to accept the shadow-D 1 signal, an input to accept the clock signal, and an output to supply the shadow-D 2 signal in the master latch pass mode;

a ninth inverter having an input to accept the shadow-D 2 signal and an output to supply the inverted shadow-D 2 signal; and,

a fourth clocked inverter circuit having an input to accept the inverted shadow-D 2 signal, an input to accept the clock signal, and an output to supply the shadow-D 2 signal in the master latch hold mode.

9. The HFML-FF of claim 8 wherein the second relay gate comprises:

a ninth clocked pass gate circuit having an input to accept the D 2 input signal, an input to accept the clock signal, and an output to supply the Q signal in the slave latch pass mode, where the Q signal has a binary value equal to the D 2 signal binary value;

a fifth clocked inverter circuit having an input to accept the inverted shadow-Q signal with a binary value equal to an inverse of the Q signal binary value, an input to accept the clock signal, and an output to supply the Q signal in a slave latch hold mode;

wherein the second shadow gate comprises:

a tenth clocked pass gate circuit having an input to accept the selected D 2 input signal, an input to accept the clock signal, and an output to supply the shadow-Q signal in the slave latch pass mode;

a tenth inverter having an input to accept the shadow-Q signal and an output to supply the inverted shadow-Q signal; and,

a sixth clocked inverter circuit having an input to accept the inverted shadow-Q signal, an input to accept the clock signal, and an output to supply the shadow-Q signal in the slave latch hold mode.

10. The HFML-FF of claim 9 wherein the first clocked inverter circuit comprises:

a ninth PMOS FET having a first S/D connected to a first dc reference voltage, a second S/D, and a gate connected to receive the D 1 signal;

a tenth PMOS FET having a first S/D connected to the second S/D of the ninth PMOS FET, a second S/D to supply the D 2 signal, and a gate to receive CK 2 ;

a ninth NMOS FET having a first S/D connected to the second S/D of the tenth PMOS FET, a second S/D, and a gate to receive CK 3 ; and,

a tenth NMOS FET having a first S/D connected to the second S/D of the ninth NMOS FET, a second S/D connected to a second dec reference voltage having a lower potential than the first de reference voltage, and a gate to accept the D 1 signal;

wherein the second clocked inverter comprises:

an eleventh PMOS FET having a first S/D connected to the first dc reference voltage, a second S/D, and a gate connected to receive the inverted shadow-D 2 signal;

a twelfth PMOS FET having a first S/D connected to the second S/D of the eleventh PMOS FET, a second S/D to supply the D 2 signal, and a gate to receive CK 1 ;

an eleventh NMOS FET having a first S/D connected to the second S/D of the twelfth PMOS FET, a second S/D, and a gate to receive CLK; and,

a twelfth NMOS FET having a first S/D connected to the second S/D of the eleventh NMOS FET, a second S/D connected to the second de reference voltage, and a gate to accept the inverted shadow-D 2 signal.

11. The HFML-FF of claim 10 wherein the third clocked inverter circuit comprises:

a thirteenth PMOS FET having a first S/D connected to a first dc reference voltage, a second S/D, and a gate connected to receive the shadow-D 1 signal;

a fourteenth PMOS FET having a first S/D connected to the second S/D of the thirteenth PMOS FET, a second S/D to supply the shadow-D 2 signal, and a gate to receive CK 2 ;

a thirteenth NMOS FET having a first S/D connected to the second S/D of the fourteenth PMOS FET, a second S/D, and a gate to receive CK 3 ; and,

a fourteenth NMOS FET having a first S/D connected to the second S/D of the thirteenth NMOS FET, a second S/D connected to the second de reference voltage, and a gate to accept the shadow-D 1 signal;

wherein the fourth clocked inverter comprises:

an fifteenth PMOS FET having a first S/D connected to the first dc reference voltage, a second S/D, and a gate connected to receive the inverted shadow-D 2 signal;

a sixteenth PMOS FET having a first S/D connected to the second S/D of the fifteenth PMOS FET, a second S/D to supply the shadow-D 2 signal, and a gate to receive CK 1 ;

a fifteenth NMOS FET having a first S/D connected to the second S/D of the sixteenth PMOS FET, a second S/D, and a gate to receive CLK; and,

a sixteenth NMOS FET having a first S/D connected to the second S/D of the fifteenth NMOS FET, a second S/D connected to the second de reference voltage, and a gate to accept the inverted shadow-D 2 signal.

12. The HFML-FF of claim 11 wherein the ninth clocked pass gate circuit comprises:

a seventeenth PMOS FET having a first source/drain (S/D) connected to the D 2 input signal, a second S/D connected to supply the Q signal, and a gate connected to receive CK 1 ;

a seventeenth NMOS FET having a first S/D connected to the first S/D of the seventeenth PMOS FET, a second S/D connected to the second S/D of the seventeenth PMOS FET, and a gate to receive CLK;

wherein the fifth clocked inverter comprises:

an eighteenth PMOS FET having a first S/D connected to the first de reference voltage, a second S/D, and a gate connected to receive the inverted shadow-Q signal;

a nineteenth PMOS FET having a first S/D connected to the second S/D of the eighteenth PMOS FET, a second S/D to supply the Q signal, and a gate to receive CLK;

an eighteenth NMOS FET having a first S/D connected to the second S/D of the nineteenth PMOS FET, a second S/D, and a gate to receive CK 1 ; and,

a nineteenth NMOS FET having a first S/D connected to the second S/D of the eighteenth NMOS FET, a second S/D connected to the second dec reference voltage, and a gate to accept the inverted shadow-Q signal.

13. The HFML-FF of claim 12 wherein the tenth clocked pass gate circuit comprises:

a twentieth PMOS FET having a first SD connected to the selected D 2 signal, a second S/D connected to supply the shadow-Q signal, and a gate connected to receive CK 1 ;

a twentieth NMOS FET having a first S/D connected to the first S/D of the twentieth PMOS FET, a second S/D connected to the second S/D of the twentieth PMOS FET, and a gate to receive CLK;

wherein the sixth clocked inverter comprises:

a twenty-first PMOS FET having a first S/D connected to the first de reference voltage, a second S/D, and a gate connected to receive the inverted shadow-Q signal;

a twenty-second PMOS FET having a first S/D connected to the second S/D of the twenty-first PMOS FET, a second S/D to supply the shadow-Q signal, and a gate to receive CLK;

a twenty-first NMOS FET having a first S/D connected to the second S/D of the twenty-second PMOS FET, a second S/D, and a gate to receive CK 1 ; and,

a twenty-second NMOS FET having a first S/D connected to the second S/D of the twenty-first NMOS FET, a second S/D connected to the second de reference voltage, and a gate to accept the inverted shadow-Q signal.

14. A hazard-free minimal-latency (HFML) latch comprising:

a relay gate having an input to accept a D 1 signal with a binary value, an input to accept a clock signal (CLK), a first clock signal (CK 1 ) equal to an inverted CLK binary value, with a first delay with respect to CLK, a second clock signal (CK 2 ) having the same binary value as CLK with a second delay greater than the first delay with respect to CLK, and a third clock signal (CK 3 ) equal to the inverted CLK binary value, with a third delay greater than the second delay with respect to CLK, an input to accept an inverted shadow-D 2 signal, and an output to supply a D 2 signal with a binary value; and,

a shadow gate having an input to accept the D 1 signal, an input to accept CLK, CK 1 , CK 2 , and CK 3 , and an output to supply the inverted shadow-D 2 signal.

15. The HFML latch of claim 14 wherein the relay gate comprises:

a first clocked pass gate circuit having an input to accept the D 1 signal, an input to accept CK 2 and CK 3 , and an output to supply the D 2 signal in a pass mode, the D 2 signal having a binary value equal to the D 1 binary value;

a first inverter to accept the inverted shadow-D 2 signal and supply a slave D 2 signal; and,

a second clocked pass gate circuit having an input to accept the slave D 2 signal, an input to accept CLK and CK 1 , and an output to supply the D 2 signal in a hold mode;

wherein the shadow gate comprises:

a third clocked pass gate circuit having an input to accept the D 1 input signal, an input to accept CK 2 and CK 3 , and an output to supply a shadow-D 2 signal in the pass mode;

a second inverter having an input to accept the shadow-D 2 signal and an output to supply the inverted shadow-D 2 signal;

a third inverter having an input to accept the inverted shadow-D 2 signal and an output to supply a shadow slave D 2 signal; and,

a fourth clocked pass gate circuit having an input to

accept the shadow slave D 2 signal, an input to accept CLK and CK 1 , and an output to supply the shadow-D 2 signal in the hold mode.

16. The HFML latch of claim 15 wherein the first clocked pass gate circuit comprises:

a first PMOS field effect transistor (FET) having a first source/drain (S/D) connected to the D 1 input signal, a second S/D connected to supply the D 2 signal, and a gate connected to receive CK 2 ;

a first NMOS FET having a first S/D connected to the first S/D of the first PMOS FET, a second S/D connected to the second S/D of the first PMOS FET, and a gate to receive CK 3 ;

wherein the second clocked pass gate circuit comprises:

a second PMOS FET having a first S/D connected to receive the slave D 2 signal, a second S/D to supply the D 2 signal, and a gate connected to receive CK 1 ;

a second NMOS FET having a first S/D connected to the first S/D of the second PMOS FET, a second S/D connected to the second S/D of the second PMOS FET, and a gate to receive CLK;

wherein the third clocked pass gate circuit comprises:

a third PMOS FET having a first SD connected to the D 1 signal, a second S/D connected to supply the shadow-D 2 signal, and a gate connected to receive CK 2 ;

a third NMOS FET having a first S/D connected to the first S/D of the third PMOS FET, a second S/D connected to the second S/D of the third PMOS FET, and a gate to receive CK 3 ;

wherein the fourth clocked pass gate circuit comprises:

a fourth PMOS FET having a first S/D connected to receive the shadow slave D 2 signal, a second S/D to supply the shadow-D 2 signal, and a gate connected to receive CK 1 ;

a fourth NMOS FET having a first S/D connected to the first S/D of the fourth PMOS FET, a second S/D connected to

the second S/D of the fourth PMOS FET, and a gate to receive CLK.

17. The HFML latch of claim 14 wherein the relay gate comprises:

a first clocked inverter circuit having an input to accept the D 1 signal, an input to accept CK 2 and CK 3 , and an output to supply the D 2 signal in the pass mode, where the D 2 signal has a binary value equal to an inverted D 1 signal binary value;

a second clocked inverter circuit having an input to accept the inverted shadow-D 2 signal, an input to accept CLK and CK 1 , and an output to supply the D 2 signal;

wherein the shadow gate comprises:

a third clocked inverter circuit having an input to accept the D 1 signal, an input to accept the CK 2 and CK 3 , and an output to supply a shadow-D 2 signal;

a fourth inverter having an input to accept the shadow-D 2 signal and an output to supply the inverted shadow-D 2 signal; and,

a fourth clocked inverter circuit having an input to accept the inverted shadow-D 2 signal, an input to accept CLK and CK 1 , and an output to supply the shadow-D 2 signal.

18. The HFML latch of claim 17 wherein the first clocked inverter circuit comprises:

a fifth PMOS FET having a first source/drain (S/D) connected to a first dec reference voltage, a second S/D, and a gate connected to receive the D 1 signal;

a sixth PMOS FET having a first S/D connected to the second S/D of the fifth PMOS FET, a second S/D to supply the D 2 signal, and a gate to receive CK 2 ;

a fifth NMOS FET having a first S/D connected to the second S/D of the sixth PMOS FET, a second S/D, and a gate to receive CK 3 ; and,

a sixth NMOS FET having a first S/D connected to the second S/D of the fifth NMOS FET, a second S/D connected to a second de reference voltage having a lower potential than the first dc reference voltage, and a gate to accept the D 1 signal;

wherein the second clocked inverter comprises:

a seventh PMOS FET having a first S/D connected to the first de reference voltage, a second S/D, and a gate connected to receive the inverted shadow-D 2 signal;

an eighth PMOS FET having a first S/D connected to the second S/D of the seventh PMOS FET, a second S/D to supply the D 2 signal, and a gate to receive CK 1 ;

a seventh NMOS FET having a first S/D connected to the second S/D of the eighth PMOS FET, a second S/D, and a gate to receive CLK; and,

an eighth NMOS FET having a first S/D connected to the second S/D of the eleventh NMOS FET, a second S/D connected to the second de reference voltage, and a gate to accept the inverted shadow-D 2 signal.

19. The HFML latch of claim 18 wherein the third clocked inverter circuit comprises:

a ninth PMOS FET having a first source/drain (S/D) connected to a first dc reference voltage, a second S/D, and a gate connected to receive the D 1 signal;

a tenth PMOS FET having a first S/D connected to the second S/D of the ninth PMOS FET, a second S/D to supply the shadow-D 2 signal, and a gate to receive CK 2 ;

a ninth NMOS FET having a first S/D connected to the second S/D of the tenth PMOS FET, a second S/D, and a gate to receive CK 3 ; and,

a tenth NMOS FET having a first S/D connected to the second S/D of the ninth NMOS FET, a second S/D connected to the second de reference voltage, and a gate to accept the D 1 signal;

wherein the fourth clocked inverter comprises:

an eleventh PMOS FET having a first S/D connected to the first dc reference voltage, a second S/D, and a gate connected to receive the inverted shadow-D 2 signal;

a twelfth FET having a first S/D connected to the second S/D of the eleventh PMOS FET, a second S/D to supply the shadow-D 2 signal, and a gate to receive CK 1 ;

an eleventh NMOS FET having a first S/D connected to the second S/D of the twelfth PMOS FET, a second S/D, and a gate to receive CLK; and,

a twelfth N MOS FET having a first S/D connected to the second S/D of the eleventh NMOS FET, a second S/D connected to the second de reference voltage, and a gate to accept the inverted shadow-D 2 signal.

Assignments (6)