Generating a pulse clock signal based on a first clock signal and a second clock signal
View Patent ↗Various aspects provide for generating a clock signal for a hold latch. A latch pulse generator generates a pulse clock signal based on a first clock signal associated with a first flip-flop component and a second clock signal associated with a second flip-flop component. A hold latch component receives the pulse clock signal generated by the latch pulse generator and generates a data signal that is transmitted to the second flip-flop component.
1. A system, comprising:
a latch pulse generator configured for generating a pulse clock signal based on a first clock signal associated with a first flip-flop component and a second clock signal associated with a second flip-flop component; and
a hold latch component configured for receiving the pulse clock signal generated by the latch pulse generator and for generating a data signal that is transmitted to the second flip-flop component.
2. The system of claim 1 , wherein the latch pulse generator comprises a first logic gate configured for generating a signal based on the first clock signal and the second clock signal.
3. The system of claim 2 , wherein the signal is received by a pulse width controller and a second logic gate configured for generating the pulse clock signal.
4. The system of claim 2 , wherein the latch pulse generator comprises a pulse width controller that modifies the signal generated by the first logic gate.
5. The system of claim 1 , wherein the latch pulse generator further comprises a set of transistors for generating a signal based on the first clock signal and the second clock signal.
6. The system of claim 5 , wherein the signal is received by a set of inverters configured for storing the signal for a period of time.
7. The system of claim 1 , wherein the latch pulse generator comprises a first logic gate configured for generating a control signal based on a first signal generated by a pulse width controller and a second signal received from a set of inverters.
8. The system of claim 7 , wherein the latch pulse generator comprises a second logic gate configured for generating the pulse clock signal based on the control signal and a signal generated based on the first clock signal and the second clock signal.
9. The system of claim 1 , wherein the pulse clock signal comprises a minimum pulse width for the hold latch component.
10. The system of claim 1 , wherein the first clock signal is a launch clock for the first flip-flop component.
11. The system of claim 1 , wherein the second clock signal is a capture clock for the second flip-flop component.
12. A method, comprising:
receiving a first clock signal associated with a first flip-flop component;
receiving a second clock signal associated with a second flip-flop component;
generating a pulse clock signal as a function of the first clock signal and the second clock signal;
generating a data signal based on the pulse clock signal; and
transmitting the data signal to the second flip-flop component.
13. The method of claim 12 , further comprising:
generating a signal as a function the first clock signal and the second clock signal via a logic gate.
14. The method of claim 13 , further comprising:
modifying the signal via a pulse width controller.
15. The method of claim 12 , further comprising:
generating a signal as a function the first clock signal and the second clock signal via a set of transistors.
16. The method of claim 15 , further comprising:
storing the signal generated via the set of transistors for a period of time.
17. The method of claim 12 , further comprising:
generating a control signal as a function of a first signal generated by a pulse width controller and a second signal received from a set of inverters.
18. The method of claim 17 , wherein the generating the pulse clock signal comprises generating the pulse clock signal as a function of the control signal and a signal generated as a function of the first clock signal and the second clock signal.
19. The method of claim 12 , wherein the generating the pulse clock signal comprises generating the pulse clock signal via a logic gate.
20. An integrated circuit chip comprising a synchronous interface, comprising:
a latch pulse generator configured for generating a pulse clock signal based on a first clock signal associated with a first flip-flop component and a second clock signal associated with a second flip-flop component; and
a hold latch component configured for receiving the pulse clock signal generated by the latch pulse generator and for generating a data signal that is transmitted to the second flip-flop component.