Split loop timing recovery
View Patent ↗Various embodiments provide systems and methods for performing clock recovery on a received signal using a split loop architecture. A split loop timing recovery apparatus is provided comprising a first path configured for performing frequency offset tracking on a signal by adjusting a receiver clock frequency to match a remote transmitter frequency associated with the signal and a second path configured for tracking random jitter on the signal.
1. A split loop timing recovery apparatus, comprising:
a first path configured for performing frequency offset tracking on a signal by adjusting a receiver clock frequency to match a remote transmitter frequency associated with the signal and further configured for performing delta sigma modulation; and
a second path configured for tracking random jitter on the signal.
2. The split loop timing recovery apparatus of claim 1 , wherein the first path has a lower bandwidth than the second path.
3. The split loop timing recovery apparatus of claim 1 , wherein the second path comprises a phase interpolator.
4. The split loop timing recovery apparatus of claim 1 wherein bandwidth associated with timing recovery is partitioned between the first path and the second path.
5. The split loop timing recovery apparatus of claim 4 , wherein the bandwidth is split between the first path and the second path based on an analysis of the signal.
6. The split loop timing recovery apparatus of claim 1 , further comprising:
a predistortion module configured for predistorting a control signal going into the second path based on a lookup table.
7. The split loop timing recovery apparatus of claim 6 , wherein the control signal is predistorted to reduce distortion of a recovered phase interpolator clock.
8. A method for performing split loop timing recovery, comprising:
performing frequency offset tracking on a signal on a first path by adjusting a receiver clock frequency to match a remote transmitter frequency associated with the signal, wherein the performing frequency offset tracking is performed via delta sigma modulation; and
tracking random jitter on the signal on a second path.
9. The method for performing split loop timing recovery of claim 8 , wherein the tracking high bandwidth random jitter is performed in a higher bandwidth path than the frequency offset tracking.
10. The method for performing split loop timing recovery of claim 9 , further comprising:
partitioning bandwidth associated with timing recovery between the frequency offset tracking and random jitter tracking performed by a phase interpolator on the second path based on an analysis of the signal.
11. The method for performing split loop timing recovery of claim 10 , wherein the partitioning bandwidth is based on an analysis of the signal.
12. The method for performing split loop timing recovery of claim 8 , further comprising:
predistorting a control signal going into a phase interpolator on the second path based on a lookup table.
13. The method of claim 12 , wherein the predistorted control signal reduces distortion of a recovered phase interpolator clock.
14. A system for split loop timing recovery, comprising:
a delta sigma modulation loop configured for performing frequency offset tracking on a signal on a first path by adjusting a receiver clock frequency to match a remote transmitter frequency associated with the signal; and
a phase interpolator loop configured for tracking random jitter on the signal on a second path.
15. The system for split loop timing recovery of claim 14 , wherein the delta sigma modulation loop is a lower bandwidth loop than the phase interpolator loop.
16. The system for split loop timing recovery of claim 14 , further comprising:
a partitioning circuit configured for partitioning bandwidth between the delta sigma modulation loop and the phase interpolator.
17. The system for split loop timing recovery of claim 16 , wherein the partitioning circuit partitions the bandwidth based on an analysis of the signal.
18. The system for split loop timing recovery of claim 14 , further comprising:
a predistortion module configured for predistorting a control signal going into the phase interpolator based on a lookup table.
19. A split loop timing recovery apparatus, comprising:
a first path configured for performing frequency offset tracking on a signal by adjusting a receiver clock frequency to match a remote transmitter frequency associated with the signal;
a second path configured for tracking random jitter on the signal; and
a predistortion module configured for predistorting a control signal going into the second path based on a lookup table.
20. The split loop timing recovery apparatus of claim 19 , wherein the control signal is predistorted to reduce distortion of a recovered phase interpolator clock.